VIN SUPPLY |
IBIAS |
VIN operating current (1) |
VSS = 0 V |
|
4.8 |
6.2 |
mA |
VSS = 0 V, VVCCDIS = 2 V |
|
0.4 |
0.55 |
mA |
ISHUTDOWN |
VIN shutdown current |
VSS = 0 V, VUVLO = 0 V |
|
16 |
40 |
µA |
VCC REGULATOR |
VCC(REG) |
VCC regulation |
No load |
6.85 |
7.6 |
8.2 |
V |
|
VCC dropout (VIN to VCC) |
VVIN = 5.5 V, No external load |
|
0.05 |
0.14 |
V |
VVIN = 6 V, ICC = 20 mA |
|
0.4 |
0.5 |
V |
|
VCC sourcing current limit |
VVCC = 0 V |
30 |
42 |
|
mA |
IVCC |
VCC operating current (1) |
VSS = 0 V, VVCCDIS = 2 V |
|
4 |
5 |
mA |
VSS = 0 V, VVCCDIS = 2 V, VVCC = 14 V |
|
5.8 |
7.3 |
mA |
|
VCC undervoltage threshold |
VCC rising |
4.7 |
4.9 |
5.15 |
V |
|
VCC undervoltage hysteresis |
|
|
0.2 |
|
V |
VCC DISABLE |
|
VCCDIS threshold |
VCCDIS rising |
1.22 |
1.25 |
1.29 |
V |
|
VCCDIS hysteresis |
|
|
0.06 |
|
V |
|
VCCDIS input current |
VVCCDIS = 0 V |
|
-20 |
|
nA |
|
VCCDIS pulldown resistance |
|
|
500 |
|
kΩ |
UVLO |
|
UVLO threshold |
UVLO rising |
1.22 |
1.25 |
1.29 |
V |
|
UVLO hysteresis current |
VUVLO = 1.4 V |
15 |
20 |
25 |
µA |
|
UVLO shutdown threshold |
UVLO falling |
0.23 |
0.3 |
|
V |
|
UVLO shutdown hysteresis |
|
|
0.1 |
|
V |
SOFT START |
ISS |
SS current source |
VSS = 0 V |
7 |
10 |
12 |
µA |
|
SS pulldown resistance |
|
|
13 |
24 |
Ω |
ERROR AMPLIFIER |
VREF |
FB reference voltage |
Measured at FB, FB = COMP |
788 |
800 |
812 |
mV |
|
FB input bias current |
VFB = 0.8 V |
|
1 |
|
nA |
VOH |
COMP output high voltage |
ISOURCE = 3 mA |
2.8 |
|
|
V |
VOL |
COMP output low voltage |
ISINK = 3 mA |
|
|
0.26 |
V |
AOL |
DC gain |
|
|
80 |
|
dB |
ƒBW |
Unity gain bandwidth |
|
|
3 |
|
MHz |
PWM COMPARATOR |
tHO(OFF) |
Forced HO Off-time |
|
260 |
320 |
440 |
ns |
tON(MIN) |
Minimum HO On-time |
VVIN = 65 V |
|
100 |
|
ns |
|
COMP to PWM comparator offset |
|
|
1.2 |
|
V |
OSCILLATOR |
|
|
|
|
|
ƒSW1 |
Frequency 1 |
RT = 25 kΩ |
180 |
200 |
220 |
kHz |
ƒSW2 |
Frequency 2 |
RT = 10 kΩ |
430 |
480 |
530 |
kHz |
|
RT output voltage |
|
|
1.25 |
|
V |
|
RT sync positive threshold |
|
2.6 |
3.2 |
3.95 |
V |
|
Sync pulse width |
|
100 |
|
|
ns |
CURRENT LIMIT |
VCS(TH) |
Cycle-by-cycle sense voltage threshold |
VRAMP = 0 V, CSG to CS |
106 |
120 |
135 |
mV |
|
CS input bias current |
VCS = 0 V |
–100 |
-66 |
|
µA |
|
CSG input bias current |
VCSG = 0 V |
–100 |
-66 |
|
µA |
|
Current sense amplifier gain |
|
|
10 |
|
V/V |
|
Hiccup mode fault timer |
|
|
256 |
|
Cycles |
RES |
IRES |
RES Current Source |
|
|
10 |
|
µA |
VRES |
RES Threshold |
RES Rising |
1.22 |
1.25 |
1.285 |
V |
DIODE EMULATION |
VIL |
DEMB input low threshold |
|
|
2 |
1.65 |
V |
VIH |
DEMB input high threshold |
|
2.95 |
2.5 |
|
V |
|
SW zero cross threshold |
|
|
–5 |
|
mV |
|
DEMB input pulldown resistance |
|
|
50 |
|
kΩ |
CURRENT MONITOR |
|
Current monitor amplifier gain |
CS to CM |
17.5 |
20.5 |
23.5 |
V/V |
|
Current monitor amplifier gain |
Drift over Temperature |
–2 |
0 |
2 |
% |
|
Zero input offset |
|
|
25 |
120 |
mV |
HO GATE DRIVER |
VOHH |
HO High-state voltage drop |
IHO = –100 mA, VOHH = VHB – VHO |
|
0.17 |
0.3 |
V |
VOLH |
HO Low-state voltage drop |
IHO = 100 mA, VOLH = VHO – VSW |
|
0.1 |
0.2 |
V |
|
HO rise time |
C-load = 1000 pF(2) |
|
6 |
|
ns |
|
HO fall time |
C-load = 1000pF(2) |
|
5 |
|
ns |
IOHH |
Peak HO source current |
VHO = 0 V, SW = 0 V, HB = 7.6 V |
|
2.2 |
|
A |
IOLH |
Peak HO sink current |
VHO = VHB = 7.6 V |
|
3.3 |
|
A |
|
HB to SW undervoltage |
|
2.56 |
2.9 |
3.32 |
V |
|
HB DC bias current |
HB – SW = 7.6 V |
|
65 |
100 |
µA |
LO GATE DRIVER |
VOHL |
LO High-state Voltage Drop |
ILO = –100 mA, VOHL = VCC-VLO |
|
0.17 |
0.27 |
V |
VOLL |
LO Low-state Voltage Drop |
ILO = 100 mA, VOLL = VLO |
|
0.1 |
0.2 |
V |
|
LO rise time |
C-load = 1000 pF(2) |
|
6 |
|
ns |
|
LO fall time |
C-load = 1000 pF(2) |
|
5 |
|
ns |
IOHL |
Peak LO source current |
VLO = 0 V |
|
2.5 |
|
A |
IOLL |
Peak LO sink current |
VLO = 7.6 V |
|
3.3 |
|
A |
THERMAL |
TSD |
Thermal shutdown |
Temperature rising |
|
165 |
|
°C |
|
Thermal shutdown hysteresis |
|
|
25 |
|
°C |