The LM5119 device is a dual synchronous buck controller intended for step-down regulator applications from a high voltage or widely varying input supply. The control method is based upon current mode control using an emulated current ramp. Current mode control provides inherent line feedforward, cycle-by-cycle current limiting and ease-of-loop compensation. The use of an emulated control ramp reduces noise sensitivity of the pulse-width modulation circuit, allowing reliable control of very small duty cycles necessary in high input voltage applications. The switching frequency is programmable from 50 kHz to 750 kHz. The LM5119 device drives external high-side and low-side NMOS power switches with adaptive dead-time control. A user-selectable diode emulation mode enables discontinuous mode operation for improved efficiency at light load conditions. A high voltage bias regulator with automatic switch-over to external bias further improves efficiency. Additional features include thermal shutdown, frequency synchronization, cycle-by-cycle and hiccup mode current limit and adjustable line undervoltage lockout. The device is available in a power enhanced leadless 32-pin WQFN package featuring an exposed die attach pad to aid thermal dissipation.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
LM5119 | WQFN (32) | 5.00 mm × 5.00 mm |
Changes from H Revision (May 2016) to I Revision
Changes from G Revision (January 2014) to H Revision
Changes from F Revision (February 2013) to G Revision
PIN | TYPE(1) | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
AGND | 12 | G | Analog ground. Return for the internal 0.8-V voltage reference and analog circuits. |
COMP1 | 10 | O | Output of the channel1 internal error amplifier. The loop compensation network must be connected between this pin and the FB1 pin. |
COMP2 | 15 | O | Output of the channel2 internal error amplifier. The loop compensation network must be connected between this pin and the FB2 pin. |
CS1 | 5 | I | Current sense amplifier input. Connect to the high side of the channel1 current sense resistor. |
CS2 | 20 | I | Current sense amplifier input. Connect to the high side of the channel2 current sense resistor. |
CSG1 | 4 | I | Kelvin ground connection to the external current sense resistor. Connect directly to the low side of the channel1 current sense resistor. |
CSG2 | 21 | I | Kelvin ground connection to the external current sense resistor. Connect directly to the low side of the channel2 current sense resistor. |
DEMB | 17 | I | Logic input that enables diode emulation when in the low state. In diode emulation mode, the low-side MOSFET is latched off for the remainder of the PWM cycle when the buck inductor current reverses direction (current flow from output to ground). When DEMB is high, diode emulation is disabled allowing current to flow in either direction through the low-side MOSFET. A 50-kΩ pulldown resistor internal to the LM5119 holds DEMB pin low and enables diode emulation if the pin is left floating. |
EN2 | 11 | I | If the EN2 pin is low, channel2 is disabled. Channel1 and all other functions remain active. The EN2 has a 50-kΩ pullup resistor to enable channel2 when the pin is left floating. |
FB1 | 9 | I | Feedback input and inverting input of the channel1 internal error amplifier. A resistor divider from the channel1 output to this pin sets the output voltage level. The regulation threshold at the FB1 pin is 0.8 V. |
FB2 | 16 | I | Feedback input and inverting input of the channel2 internal error amplifier. A resistor divider from the channel2 output to this pin sets the output voltage level. The regulation threshold at the FB2 pin is 0.8 V. |
HB1 | 30 | P | High-side driver supply for bootstrap gate drive. Connect to the cathode of the channel1 external bootstrap diode and to the bootstrap capacitor. The bootstrap capacitor supplies current to charge the high-side MOSFET gate and must be placed as close to controller as possible. |
HB2 | 27 | P | High-side driver supply for bootstrap gate drive. Connect to the cathode of the channel2 external bootstrap diode and to the bootstrap capacitor. The bootstrap capacitor supplies current to charge the high-side MOSFET gate and must be placed as close to the controller as possible. |
HO1 | 31 | O | High-side MOSFET gate drive output. Connect to the gate of the channel1 high-side MOSFET through a short, low inductance path. |
HO2 | 26 | O | High-side MOSFET gate drive output. Connect to the gate of the channel2 high-side MOSFET through a short, low inductance path. |
LO1 | 2 | O | Low-side MOSFET gate drive output. Connect to the gate of the channel1 low-side synchronous MOSFET through a short, low inductance path. |
LO2 | 23 | O | Low-side MOSFET gate drive output. Connect to the gate of the channel2 low-side synchronous MOSFET through a short, low inductance path. |
PGND1 | 3 | G | Power ground return pin for low-side MOSFET gate driver. Connect directly to the low side of the channel1 current sense resistor. |
PGND2 | 22 | G | Power ground return pin for low-side MOSFET gate driver. Connect directly to the low side of the channel2 current sense resistor. |
RAMP1 | 6 | I | PWM ramp signal. An external resistor and capacitor connected between the SW1 pin, the RAMP1 pin and the AGND pin sets the channel1 PWM ramp slope. Proper selection of component values produces a RAMP1 signal that emulates the current in the buck inductor. |
RAMP2 | 19 | I | PWM ramp signal. An external resistor and capacitor connected between the SW2 pin, the RAMP2 pin and the AGND pin sets the channel2 PWM ramp slope. Proper selection of component values produces a RAMP2 signal that emulates the current in the buck inductor. |
RES | 14 | O | The restart timer pin for an external capacitor that configures the hiccup mode current limiting. A capacitor on the RES pin determines the time the controller remains off before automatically restarting in hiccup mode. The two regulator channels operate independently. One channel may operate in normal mode while the other is in hiccup mode overload protection. The hiccup mode commences when either channel experiences 256 consecutive PWM cycles with cycle-by-cycle current limiting. After this occurs, a 10-µA current source charges the RES pin capacitor to the 1.25-V threshold which restarts the overloaded channel. |
RT | 13 | I | The internal oscillator is set with a single resistor between RT and AGND. The recommended maximum oscillator frequency is 1.5 MHz which corresponds to a maximum switching frequency of 750 kHz for either channel. The internal oscillator can be synchronized to an external clock by coupling a positive pulse into RT through a small coupling capacitor. |
SS1 | 7 | I | An external capacitor and an internal 10-µA current source set the ramp rate of the channel1 error amp reference. The SS1 pin is held low when VCC1 or VCC2 < 4.9 V, UVLO < 1.25 V or during thermal shutdown. |
SS2 | 18 | I | An external capacitor and an internal 10-µA current source set the ramp rate of the channel2 error amp reference. The SS2 pin is held low when VCC1 or VCC2 < 4.9 V, UVLO < 1.25 V or during thermal shutdown. |
SW1 | 32 | I/O | Switching node of the buck regulator. Connect to channel1 bootstrap capacitor, the source terminal of the high-side MOSFET and the drain terminal of the low-side MOSFET. |
SW2 | 25 | I/O | Switching node of the buck regulator. Connect to channel2 bootstrap capacitor, the source terminal of the high-side MOSFET and the drain terminal of the low-side MOSFET. |
UVLO | 28 | I | Undervoltage lockout programming pin. If the UVLO pin is below 0.4 V, the regulator is in the shutdown mode with all function disabled. If the UVLO pin is greater than 0.4 V and below 1.25 V, the regulator is in standby mode with the VCC regulators operational, the SS pins grounded and no switching at the HO and LO outputs. If the UVLO pin voltage is above 1.25 V, the SS pins are allowed to ramp and pulse width modulated gate drive signals are delivered at the LO and HO pins. A 20-µA current source is enabled when UVLO exceeds 1.25 V and flows through the external UVLO resistors to provide hysteresis. |
VCCDIS | 8 | I | Optional input that disables the internal VCC regulators when external biasing is supplied. If VCCDIS > 1.25 V, the internal VCC regulators are disabled. The externally supplied bias must be coupled to the VCC pins through a diode. VCCDIS has a 500-kΩ pulldown resistor to ground to enable the VCC regulators when the pin is left floating. The pulldown resistor can be overridden by pulling VCCDIS above 1.25 V with a resistor divider connected to the external bias supply. |
VIN | 29 | P | Supply voltage input source for the VCC regulators. |
Thermal Pad | — | Thermal pad of WQFN package. No internal electrical connections. Solder to the ground plane to reduce thermal resistance. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
VIN to AGND | –0.3 | 75 | V | |
SW1, SW2 to AGND | –3 | 75 | V | |
HB1 to SW1, HB2 to SW2 | –0.3 | 15 | V | |
VCC1, VCC2 to AGND (2) | –0.3 | 15 | V | |
FB1, FB2, DEMB, RES, VCCDIS, UVLO to AGND | –0.3 | 15 | V | |
HO1 to SW1, HO2 to SW2 | –0.3 | HB + 0.3 | V | |
LO1, LO2 to AGND | –0.3 | VCC + 0.3 | V | |
SS1, SS2 to AGND | –0.3 | 7 | V | |
EN2, RT to AGND | –0.3 | 7 | V | |
CS1, CS2, CSG1, CSG2 to AGND | –0.3 | 0.3 | V | |
PGND to AGND | –0.3 | 0.3 | V | |
Junction temperature, TJ | 150 | °C | ||
Storage temperature, Tstg | –55 | 150 | °C |