SNVS676I August   2010  – April  2018 LM5119

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Application Circuit
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  High Voltage Start-Up Regulator
      2. 7.3.2  UVLO
      3. 7.3.3  Enable 2
      4. 7.3.4  Oscillator and Sync Capability
      5. 7.3.5  Error Amplifiers and PWM Comparators
      6. 7.3.6  Ramp Generator
      7. 7.3.7  Current Limit
      8. 7.3.8  Hiccup Mode Current Limiting
      9. 7.3.9  Soft Start
      10. 7.3.10 HO and LO Output Drivers
      11. 7.3.11 Maximum Duty Cycle
      12. 7.3.12 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Diode Emulation
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Miscellaneous Functions
      2. 8.1.2 Interleaved Two-Phase Operation
      3. 8.1.3 Interleaved 4-Phase Operation
    2. 8.2 Typical Applications
      1. 8.2.1 Dual-output Design Example
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Timing Resistor
          2. 8.2.1.2.2  Output Inductor
          3. 8.2.1.2.3  Current Sense Resistor
          4. 8.2.1.2.4  Ramp Resistor and Ramp Capacitor
          5. 8.2.1.2.5  Output Capacitors
          6. 8.2.1.2.6  Input Capacitors
          7. 8.2.1.2.7  VCC Capacitor
          8. 8.2.1.2.8  Bootstrap Capacitor
          9. 8.2.1.2.9  Soft-Start Capacitor
          10. 8.2.1.2.10 Restart Capacitor
          11. 8.2.1.2.11 Output Voltage Divider
          12. 8.2.1.2.12 UVLO Divider
            1. 8.2.1.2.12.1 MOSFET Selection
          13. 8.2.1.2.13 MOSFET Snubber
          14. 8.2.1.2.14 Error Amplifier Compensation
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Two-Phase Design Example
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Switching Jitter Root Causes and Solutions
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.1.2.12.1 MOSFET Selection

Selection of the power MOSFETs is governed by the same tradeoffs as switching frequency. Breaking down the losses in the high-side and low-side MOSFETs is one way to compare the relative efficiencies of different devices. When using discrete SO-8 MOSFETs, generally the output current capability range is 2 A to 10 A. Losses in the power MOSFETs can be broken down into conduction loss, gate charging loss, and switching loss. Conduction loss PDC is approximately Equation 36 and the example (Equation 37).

Equation 36. LM5119 30124060.gif
Equation 37. LM5119 30124061.gif

where

  • D is the duty cycle
  • The 1.3 factor accounts for the increase in MOSFET on-resistance due to heating

Alternatively, the factor of 1.3 can be eliminated and the high temperature ON-resistance of the MOSFET can be estimated using the RDS(ON) vs Temperature curves in the MOSFET datasheet. Gate charging loss, PGC, results from the current driving the gate capacitance of the power MOSFETs and is approximated with Equation 38.

Equation 38. LM5119 30124062.gif

where

  • Qg refers to the total gate charge of an individual MOSFET
  • n is the number of MOSFETs

Gate charge loss differs from conduction and switching losses in that the actual dissipation occurs in the LM5119 and not in the MOSFET itself. Further loss in the LM5119 is incurred if the gate driving current is supplied by the internal linear regulator. In this example, VCC is supplied from the 10-V output through a diode to minimize the loss of the internal linear regulator.

Switching loss occurs during the brief transition period as the MOSFET turns on and off. During the transition period both current and voltage are present in the channel of the MOSFET. The switching loss can be approximated with Equation 39.

Equation 39. LM5119 30124063.gif

where

  • tR and tF are the rise and fall times of the MOSFET

The rise and fall times are usually mentioned in the MOSFET datasheet or can be empirically observed with an oscilloscope. Switching loss is calculated for the high-side MOSFET only. Switching loss in the low-side MOSFET is negligible because the body diode of the low-side MOSFET turns on before the MOSFET itself, minimizing the voltage from drain to source before turnon. For this example, the maximum drain-to-source voltage applied to either MOSFET is 55 V. The selected MOSFETs must be able to withstand 55 V plus any ringing from drain to source, and be able to handle at least the VCC voltage plus any ringing from gate to source. A good choice of MOSFET for the 55-V input design example is the PSMN5R5. It has an RDS(ON) of 5.2 mΩ and total gate charge of 56 nC. In applications where a high step-down ratio is maintained in normal operation, efficiency may be optimized by choosing a high-side MOSFET with lower Qg, and low-side MOSFET with lower RDS(ON).