VIN SUPPLY |
ISHUTDOWN |
VIN shutdown current |
VUVLO = 0 V |
|
9 |
17 |
µA |
IBIAS |
VIN operating current (exclude the current into RT resistor) |
VUVLO = 2 V, non-switching |
|
4 |
5 |
mA |
VCC REGULATOR |
VCC(REG) |
VCC regulation |
No load |
6.9 |
7.6 |
8.3 |
V |
|
VCC dropout (VIN to VCC) |
VVIN = 4.5 V, no external load |
|
|
0.25 |
V |
VVIN = 4.5 V, IVCC = 25 mA |
|
0.28 |
0.5 |
V |
|
VCC sourcing current limit |
VVCC = 0 V |
50 |
62 |
|
mA |
IVCC |
VCC operating current (exclude the current into RT resistor) |
VVCC = 8.3 V |
|
3.5 |
5 |
mA |
VVCC = 12 V |
|
4.5 |
8 |
mA |
|
VCC undervoltage threshold |
VCC rising, VVIN = 4.5 V |
3.9 |
4 |
4.1 |
V |
VCC falling, VVIN = 4.5 V |
|
|
3.7 |
V |
|
VCC undervoltage hysteresis |
|
|
0.385 |
|
V |
UNDERVOLTAGE LOCKOUT |
|
UVLO threshold |
UVLO rising |
1.17 |
1.2 |
1.23 |
V |
|
UVLO hysteresis current |
VUVLO = 1.4 V |
7 |
10 |
13 |
µA |
|
UVLO standby enable threshold |
UVLO rising |
0.3 |
0.4 |
0.5 |
V |
|
UVLO standby enable hysteresis |
|
|
0.1 |
0.125 |
V |
MODE |
|
Diode emulation mode threshold |
MODE rising |
1.2 |
1.24 |
1.28 |
V |
|
Diode emulation mode hysteresis |
|
|
0.1 |
|
V |
|
Default MODE voltage |
|
145 |
155 |
170 |
mV |
|
Default skip cycle threshold |
COMP rising, measured at COMP |
|
1.290 |
|
V |
COMP falling, measured at COMP |
|
1.245 |
|
V |
|
Skip cycle hysteresis |
Measured at COMP |
|
40 |
|
mV |
ERROR AMPLIFIER |
VREF |
FB reference voltage |
Measured at FB, VFB = VCOMP |
1.188 |
1.2 |
1.212 |
V |
|
FB input bias current |
VFB = VREF |
|
5 |
|
nA |
VOH |
COMP output high voltage |
ISOURCE = 2 mA, VVCC = 4.5 V |
2.75 |
|
|
V |
ISOURCE = 2 mA, VVCC = 12 V |
3.4 |
|
|
V |
VOL |
COMP output low voltage |
ISINK = 2 mA |
|
|
0.25 |
V |
AOL |
DC gain |
|
|
80 |
|
dB |
fBW |
Unity gain bandwidth |
|
|
3 |
|
MHz |
|
Slave mode threshold |
FB rising |
|
2.7 |
3.4 |
V |
OSCILLATOR |
fSW1 |
Switching frequency 1 |
RT = 20 kΩ |
400 |
450 |
500 |
kHz |
fSW2 |
Switching frequency 2 |
RT = 10 kΩ |
775 |
875 |
975 |
kHz |
|
RT output voltage |
|
|
1.2 |
|
V |
|
RT sync rising threshold |
RT rising |
|
2.5 |
2.9 |
V |
|
RT sync falling threshold |
RT falling |
1.6 |
2 |
|
V |
|
Minimum sync pulse width |
|
100 |
|
|
ns |
SYNCOUT |
|
SYNCOUT high-state voltage |
ISYNCOUT = –1 mA |
3.3 |
4.3 |
|
V |
|
SYNCOUT low-state voltage |
ISYNCOUT = 1 mA |
|
0.15 |
0.25 |
V |
OPT |
|
Synchronization selection threshold |
OPT rising |
2 |
3 |
4 |
V |
SLOPE COMPENSATION |
|
SLOPE output voltage |
|
1.17 |
1.2 |
1.23 |
V |
VSLOPE |
Slope compensation amplitude |
RSLOPE = 20 kΩ, fSW = 100 kHz, 50% duty cycle, TJ = –40°C to 125°C |
1.375 |
1.65 |
1.925 |
V |
RSLOPE= 20 kΩ, fSW= 100 kHz, 50% duty cycle, TJ = 25°C |
1.4 |
1.65 |
1.9 |
V |
SOFT START |
ISS-SOURCE |
SS current source |
VSS = 0 V |
7.5 |
10 |
12 |
µA |
|
SS discharge switch RDS-ON |
|
|
13 |
|
Ω |
PWM COMPARATOR |
tLO-OFF |
Forced LO off-time |
VVCC = 5.5 V |
|
330 |
400 |
ns |
VVCC = 4.5 V |
|
560 |
750 |
ns |
tON-MIN |
Minimum LO on-time |
RSLOPE = 20 kΩ |
|
150 |
|
ns |
RSLOPE = 200 kΩ |
|
300 |
|
ns |
|
COMP to PWM voltage drop |
TJ = –40°C to 125°C |
0.95 |
1.1 |
1.25 |
V |
TJ = 25°C |
1 |
1.1 |
1.2 |
V |
CURRENT SENSE / CYCLE-BY-CYCLE CURRENT LIMIT |
VCS-TH1 |
Cycle-by-cycle current limit threshold |
CSP to CSN, TJ = –40°C to 125°C |
65.5 |
75 |
87.5 |
mV |
CSP to CSN, TJ = 25°C |
67 |
75 |
86 |
mV |
VCS-ZCD |
Zero cross detection threshold |
CSP to CSN, rising |
|
7 |
|
mV |
CSP to CSN, falling |
0.5 |
6 |
12 |
mV |
|
Current sense amplifier gain |
|
|
10 |
|
V/V |
ICSP |
CSP input bias current |
|
|
12 |
|
µA |
ICSN |
CSN input bias current |
|
|
11 |
|
µA |
|
Bias current matching |
ICSP – ICSN |
–1.75 |
1 |
3.75 |
µA |
ICSP – ICSN (LM5122Z only) |
–2.5 |
1 |
8.75 |
|
CS to LO delay |
Current sense / current limit delay |
|
150 |
|
ns |
HICCUP-MODE RESTART |
VRES |
Restart threshold |
RES rising |
1.15 |
1.2 |
1.25 |
V |
VHCP-UPPER |
Hiccup counter upper threshold |
RES rising |
|
4.2 |
|
V |
RES rising, VVIN = VVCC = 4.5 V |
|
3.6 |
|
V |
VHCP-LOWER |
Hiccup counter lower threshold |
RES falling |
|
2.15 |
|
V |
RES falling, VVIN = VVCC = 4.5 V |
|
1.85 |
|
V |
IRES-SOURCE1 |
RES current source1 |
Fault-state charging current |
20 |
30 |
40 |
µA |
IRES-SINK1 |
RES current sink1 |
Normal-state discharging current |
|
5 |
|
µA |
IRES-SOURCE2 |
RES current source2 |
Hiccup-mode off-time charging current |
|
10 |
|
µA |
IRES-SINK2 |
RES current sink2 |
Hiccup-mode off-time discharging current |
|
5 |
|
µA |
|
Hiccup cycle |
|
|
8 |
|
Cycles |
|
RES discharge switch RDS-ON |
|
|
40 |
|
Ω |
|
Ratio of hiccup mode off-time to restart delay time |
|
|
122 |
|
|
HO GATE DRIVER |
VOHH |
HO high-state voltage drop |
IHO = –100 mA, VOHH = VBST –VHO |
|
0.15 |
0.24 |
V |
VOLH |
HO low-state voltage drop |
IHO = 100 mA, VOLH = VHO –VSW |
|
0.1 |
0.18 |
V |
|
HO rise time (10% to 90%) |
CLOAD = 4700 pF, VBST = 12 V |
|
25 |
|
ns |
|
HO fall time (90% to 10%) |
CLOAD = 4700 pF, VBST = 12 V |
|
20 |
|
ns |
IOHH |
Peak HO source current |
VHO = 0 V, VSW = 0 V, VBST = 4.5 V |
|
0.8 |
|
A |
VHO = 0 V, VSW = 0 V, VBST = 7.6 V |
|
1.9 |
|
A |
IOLH |
Peak HO sink current |
VHO = VBST = 4.5 V |
|
1.9 |
|
A |
VHO = VBST= 7.6 V |
|
3.2 |
|
A |
IBST |
BST charge pump sourcing current |
VVIN = VSW = 9. V , VBST - VSW = 5 V |
100 |
200 |
|
µA |
|
BST charge pump regulation |
BST to SW, IBST= –70 μA, VVIN = VSW = 9 V |
5.3 |
6.2 |
6.75 |
V |
BST to SW, IBST = –70 μA, VVIN = VSW = 12 V |
7 |
8.5 |
9 |
V |
|
BST to SW undervoltage |
|
2 |
3 |
3.5 |
V |
|
BST DC bias current |
VBST – VSW = 12 V, VSW = 0 V |
|
30 |
45 |
µA |
LO GATE DRIVER |
VOHL |
LO high-state voltage drop |
ILO = –100 mA, VOHL = VVCC –VLO |
|
0.15 |
0.25 |
V |
VOLL |
LO low-state voltage drop |
ILO = 100 mA, VOLL = VLO |
|
0.1 |
0.17 |
V |
|
LO rise time (10% to 90%) |
CLOAD = 4700 pF |
|
25 |
|
ns |
|
LO fall time (90% to 10%) |
CLOAD = 4700 pF |
|
20 |
|
ns |
IOHL |
Peak LO source current |
VLO = 0 V, VVCC = 4.5 V |
|
0.8 |
|
A |
VLO = 0 V |
|
2 |
|
A |
IOLL |
Peak LO sink current |
VLO = VVCC = 4.5 V |
|
1.8 |
|
A |
VLO = VVCC |
|
3.2 |
|
A |
SWITCHING CHARACTERISTICS |
tDLH |
LO fall to HO rise delay |
No load, 50% to 50% |
50 |
80 |
115 |
ns |
No load, 50% to 50% (LM5122Z only) |
50 |
80 |
145 |
tDHL |
HO fall to LO rise delay |
No load, 50% to 50% |
60 |
80 |
105 |
ns |
THERMAL |
TSD |
Thermal shutdown |
Temperature rising |
|
165 |
|
°C |
|
Thermal shutdown hysteresis |
|
|
25 |
|
°C |