Refer to the PDF data sheet for device specific package drawings
The LM5122ZA is a multi-phase capable synchronous boost controller intended for high-efficiency synchronous boost regulator applications. The control method is based upon peak-current-mode control. Current-mode control provides inherent line feed forward, cycle-by-cycle current limiting, and ease of loop compensation.
The switching frequency is programmable up to 1 MHz. Higher efficiency is achieved by two robust N-channel MOSFET gate drivers with adaptive dead-time control. A user-selectable diode-emulation mode also enables discontinuous-mode operation for improved efficiency at light load conditions.
An internal charge pump allows 100% duty cycle for high-side synchronous switch (bypass operation). A 180° phase shifted clock output enables easy multi-phase interleaved configuration. Additional features include thermal shutdown, frequency synchronization, hiccup-mode current limit, and adjustable line undervoltage lockout.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
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LM5122ZA | HTSSOP (24) | 7.80 mm × 4.40 mm |
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Changes from * Revision (May 2018) to A Revision
PIN | TYPE(1) | DESCRIPTION | |
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NAME | NO. | ||
AGND | 11 | G | \\Analog ground connection. Return for the internal voltage reference and\ analog circuits. |
BST | 24 | P | High-side driver supply for bootstrap gate drive. Connect to the cathode of the external bootstrap diode and to the bootstrap capacitor. The bootstrap capacitor supplies current to charge the high-side N-channel MOSFET gate and should be placed as close to controller as possible. An internal BST charge pump supplies 200-µA current into bootstrap capacitor for bypass operation. |
COMP | 13 | O | Output of the internal error amplifier. Connect the loop compensation network between this pin and the FB pin. |
CSN | 4 | I | Inverting input of current sense amplifier. Connect to the negative-side of the current sense resistor. |
CSP | 5 | I | Non-inverting input of current sense amplifier. Connect to the positive-side of the current sense resistor. |
FB | 12 | I | Feedback. Inverting input of the internal error amplifier. A resistor divider from the output to this pin sets the output voltage level. The regulation threshold at the FB pin is 1.2 V. The controller is configured as slave mode if the FB pin voltage is above 2.7 V at initial power-on. |
HO | 23 | O | High-side N-channel MOSFET gate drive output. Connect to the gate of the high-side synchronous N-channel MOSFET switch through a short, low inductance path. |
LO | 18 | O | Low-side N-channel MOSFET gate drive output. Connect to the gate of the low-side N-channel MOSFET switch through a short, low inductance path. |
MODE | 15 | I | Switching mode selection pin. 700-kΩ pullup and 100-kΩ pulldown resistor internal hold MODE pin to 0.15 V as a default. By adding external pullup or pulldown resistor, MODE pin voltage can be programmed. When MODE pin voltage is greater than 1.2-V diode emulation mode threshold, forced PWM mode is enabled, allowing current to flow in either direction through the high-side N-channel MOSFET switch. When MODE pin voltage is less than 1.2 V, the controller works in diode emulation mode. Skip cycle comparator is activated as a default. If MODE pin is grounded, the controller still operates in diode emulation mode, but the skip cycle comparator will not be triggered in normal operation, this enables pulse skipping operation at light load. |
OPT | 2 | I | Clock synchronization selection pin. This pin also enables/disables SYNCOUT related with master/slave configuration. The OPT pin should not be left floating. |
PGND | 17 | G | Power ground connection pin for low-side N-channel MOSFET gate driver. Connect directly to the source terminal of the low-side N-channel MOSFET switch. |
RES | 16 | O | The restart timer pin for an external capacitor that configures hiccup mode off-time and restart delay during over load conditions. Connect directly to the AGND when hiccup mode operation is not required. |
SLOPE | 14 | I | Slope compensation is programmed by a single resistor between SLOPE and the AGND. |
SS | 9 | I | Soft-start programming pin. An external capacitor and an internal 10-μA current source set the ramp rate of the internal error amplifier reference during soft-start. |
SW | 22 | I/O | Switching node of the boost regulator. Connect to the bootstrap capacitor, the source terminal of the high-side N-channel MOSFET switch and the drain terminal of the low-side N-channel MOSFET switch through short, low inductance paths. |
SYNCIN/RT | 10 | I | The internal oscillator frequency is programmed by a single resistor between RT and the AGND. The internal oscillator can be synchronized to an external clock by applying a positive pulse signal into this SYNCIN pin. The recommended maximum internal oscillator frequency in master configuration is 2 MHz which leads to 1 MHz maximum switching frequency. |
SYNCOUT | 1 | O | Clock output pin. SYNCOUT provides 180° shifted clock output for an interleaved operation. SYNCOUT pin can be left floating when it is not used. See Slave Mode and SYNCOUT section. |
UVLO | 8 | I | Undervoltage lockout programming pin. If the UVLO pin is below 0.4 V, the regulator is in the shutdown mode with all functions disabled. If the UVLO pin voltage is greater than 0.4 V and below 1.2 V, the regulator is in standby mode with the VCC regulator operational and no switching at the HO and LO outputs. If the UVLO pin voltage is above 1.2 V, the start-up sequence begins. A 10-μA current source at UVLO pin is enabled when UVLO exceeds 1.2 V and flows through the external UVLO resistors to provide hysteresis. The UVLO pin should not be left floating. |
VCC | 19 | P/O/I | VCC bias supply pin. Locally decouple to PGND using a low ESR/ESL capacitor located as close as possible to controller. |
VIN | 6 | P/I | Supply voltage input source for the VCC regulator. Connect to input capacitor and source power supply connection with short, low impedance paths. |
EP | N/A | Exposed pad of the package. Must be soldered to the large ground plane to reduce thermal resistance. | |
NC | 3, 7, 20, 21 | No electrical contact |
MIN | MAX | UNIT | ||
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Input | VIN, CSP, CSN | –0.3 | 75 | V |
BST to SW, FB, MODE, UVLO, OPT, VCC(2) | –0.3 | 15 | V | |
SW | –5 | 105 | V | |
BST | –0.3 | 115 | V | |
SS, SLOPE, SYNCIN/RT | –0.3 | 7 | V | |
CSP to CSN, PGND | –0.3 | 0.3 | V | |
Output(3) | HO to SW | –0.3 | BST to SW + 0.3 | V |
LO | –0.3 | VCC + 0.3 | V | |
COMP, RES, SYNCOUT | –0.3 | 7 | V | |
Thermal | Junction temperature, TJ | –40 | 150 | °C |
Storage temperature, Tstg | –55 | 150 | °C |