SNVSC77 December   2024 LM5125-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Device Configuration (CFG0-pin, CFG1-pin, CFG2-pin)
      2. 6.3.2  Switching Frequency and Synchronization (SYNCIN)
      3. 6.3.3  Dual Random Spread Spectrum (DRSS)
      4. 6.3.4  Operation Modes (BYPASS, DEM, FPWM)
      5. 6.3.5  Dual- and Multi-phase Operation
      6. 6.3.6  BIAS (BIAS-pin)
      7. 6.3.7  Soft Start (SS-pin)
      8. 6.3.8  VOUT Programming (VOUT, ATRK, DTRK)
      9. 6.3.9  Protections
      10. 6.3.10 VOUT Overvoltage Protection (OVP)
      11. 6.3.11 Thermal Shutdown (TSD)
      12. 6.3.12 Power-Good Indicator (PGOOD-pin)
      13. 6.3.13 Current Sensing, Peak Current Limit, and Slope Compensation (CSP1, CSP2, CSN1, CSN2)
      14. 6.3.14 Current Sense Programming (CSP1, CSP2, CSN1, CSN2)
      15. 6.3.15 Input Current Limit and Monitoring (ILIM, IMON, DLY)
      16. 6.3.16 Signal Deglitch Overview
      17. 6.3.17 MOSFET Drivers, Integrated Boot Diode, and Hiccup Mode Fault Protection (LOx, HOx, HBx-pin)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown State
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Feedback Compensation
    2. 7.2 Typical Application
      1. 7.2.1 Application
      2. 7.2.2 Design Requirements
      3. 7.2.3 Detailed Design Procedure
        1. 7.2.3.1  Determine the Total Phase Number
        2. 7.2.3.2  Determining the Duty Cycle
        3. 7.2.3.3  Timing Resistor RT
        4. 7.2.3.4  Inductor Selection Lm
        5. 7.2.3.5  Current Sense Resistor Rcs
        6. 7.2.3.6  Current Sense Filter RCSFP, RCSFN, CCS
        7. 7.2.3.7  Low-Side Power Switch QL
        8. 7.2.3.8  High-Side Power Switch QH and Additional Parallel Schottky Diode
        9. 7.2.3.9  Snubber Components
        10. 7.2.3.10 Vout Programming
        11. 7.2.3.11 Input Current Limit (ILIM/IMON)
        12. 7.2.3.12 UVLO Divider
        13. 7.2.3.13 Soft Start
        14. 7.2.3.14 CFG Settings
        15. 7.2.3.15 Output Capacitor Cout
        16. 7.2.3.16 Input Capacitor Cin
        17. 7.2.3.17 Bootstrap Capacitor
        18. 7.2.3.18 VCC Capacitor CVCC
        19. 7.2.3.19 BIAS Capacitor
        20. 7.2.3.20 VOUT Capacitor
        21. 7.2.3.21 Loop Compensation
      4. 7.2.4 Application Curves
        1. 7.2.4.1 Efficiency
        2. 7.2.4.2 Steady State Waveforms
        3. 7.2.4.3 Step Load Response
        4. 7.2.4.4 Sync Operation
        5. 7.2.4.5 Thermal Performance
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Tape and Reel Information
    2.     85

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)

6.3.15 Input Current Limit and Monitoring (ILIM, IMON, DLY)

The average input current can be monitored at the IMON-pin. Phase 1 and phase 2 input current is summed up generating a source current at the IMON pin, which is converted to a voltage by the resistor RIMON. The resulting voltage VIMON is calculated according to Equation 12, the required resistor RIMON according to Equation 11. VIMON can regulate up to 3V and is self protecting not reaching the absolute maximum value.

Equation 11. RIMON= VIMON(RCS1+RCS2) ×IIN×GIMON+2×IOFFSET
Equation 12. VIMON= ((RCS1+RCS2)×IIN×GIMON+2×IOFFSET)×RIMON

RCS1 and RCS2 are the respective phase sense resistors. IIN the input current, GIMON the transconductance gain and IOFFSET the offset current given in the electrical characteristics table.

The average input current can be limited by choosing an appropriate resistor connected to the ILIM-pin. VOUT is then regulated down until the set average input current limit is reached. The DLY-pin capacitor CDLY adds an additional delay time tDLY to activate and deactivate the average input current limit (see Average Current Limit). When the ILIM-pin voltage reaches the threshold VILIM (typical 1V) the source current IDLY is activated charging up the DLY-pin capacitor CDLY. The DLY-pin voltage VDLY rises until VDLY_peak_rise is reached, which activates the average input current limit. The ILIM-pin voltage is regulated to VILIM and the input current is regulated down to the average input current limit set by RILIM resulting in a VOUT drop. To exit the avarage current limit regulation the output load has to decrease, which causes VOUT to rise and VILIM to fall below VILIM_reset (typical 0.9V). VILIM_reset activates the sink current IDLY, which discharges the DLY-pin capacitor CDLY. When VDLY reaches VDLY_peak_fall the average input current limit is deactivated and the DLY-pin is discharged to VDLY_valley. The required resistor RILIM is calculated according to Equation 13.

Equation 13. R I L I M =   1 V ( R C S 1 + R C S 2 ) × I I N _ L I M × G I M O N + 2 × I O F F S E T
Equation 14. tDLY= 2.6 ×CDLY5×10-6
Equation 15. CDLY=tDLY×5×10-62.6
LM5125-Q1 Average Current Limit Figure 6-19 Average Current Limit