SNVSC77 December   2024 LM5125-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Device Configuration (CFG0-pin, CFG1-pin, CFG2-pin)
      2. 6.3.2  Switching Frequency and Synchronization (SYNCIN)
      3. 6.3.3  Dual Random Spread Spectrum (DRSS)
      4. 6.3.4  Operation Modes (BYPASS, DEM, FPWM)
      5. 6.3.5  Dual- and Multi-phase Operation
      6. 6.3.6  BIAS (BIAS-pin)
      7. 6.3.7  Soft Start (SS-pin)
      8. 6.3.8  VOUT Programming (VOUT, ATRK, DTRK)
      9. 6.3.9  Protections
      10. 6.3.10 VOUT Overvoltage Protection (OVP)
      11. 6.3.11 Thermal Shutdown (TSD)
      12. 6.3.12 Power-Good Indicator (PGOOD-pin)
      13. 6.3.13 Current Sensing, Peak Current Limit, and Slope Compensation (CSP1, CSP2, CSN1, CSN2)
      14. 6.3.14 Current Sense Programming (CSP1, CSP2, CSN1, CSN2)
      15. 6.3.15 Input Current Limit and Monitoring (ILIM, IMON, DLY)
      16. 6.3.16 Signal Deglitch Overview
      17. 6.3.17 MOSFET Drivers, Integrated Boot Diode, and Hiccup Mode Fault Protection (LOx, HOx, HBx-pin)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown State
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Feedback Compensation
    2. 7.2 Typical Application
      1. 7.2.1 Application
      2. 7.2.2 Design Requirements
      3. 7.2.3 Detailed Design Procedure
        1. 7.2.3.1  Determine the Total Phase Number
        2. 7.2.3.2  Determining the Duty Cycle
        3. 7.2.3.3  Timing Resistor RT
        4. 7.2.3.4  Inductor Selection Lm
        5. 7.2.3.5  Current Sense Resistor Rcs
        6. 7.2.3.6  Current Sense Filter RCSFP, RCSFN, CCS
        7. 7.2.3.7  Low-Side Power Switch QL
        8. 7.2.3.8  High-Side Power Switch QH and Additional Parallel Schottky Diode
        9. 7.2.3.9  Snubber Components
        10. 7.2.3.10 Vout Programming
        11. 7.2.3.11 Input Current Limit (ILIM/IMON)
        12. 7.2.3.12 UVLO Divider
        13. 7.2.3.13 Soft Start
        14. 7.2.3.14 CFG Settings
        15. 7.2.3.15 Output Capacitor Cout
        16. 7.2.3.16 Input Capacitor Cin
        17. 7.2.3.17 Bootstrap Capacitor
        18. 7.2.3.18 VCC Capacitor CVCC
        19. 7.2.3.19 BIAS Capacitor
        20. 7.2.3.20 VOUT Capacitor
        21. 7.2.3.21 Loop Compensation
      4. 7.2.4 Application Curves
        1. 7.2.4.1 Efficiency
        2. 7.2.4.2 Steady State Waveforms
        3. 7.2.4.3 Step Load Response
        4. 7.2.4.4 Sync Operation
        5. 7.2.4.5 Thermal Performance
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Tape and Reel Information
    2.     85

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)

7.2.3.10 Vout Programming

For fixed output voltage, VOUT can be programmed by connecting a resistor to ATRK/DTRK and turn on precise internal 20μA current source.

Equation 43. R A T R K = V o u t _ m a x 6 V × 10 k Ω = 75 k Ω

For class-H audio application, Vout can be adjusted to optimize the efficiency. Analog tracking or digital tracking can be applied with ATRK/DTRK.

For analog tracking, apply a voltage to ATRK/DTRK to program Vout. The voltage can be found as:

Equation 44. V A T R K _ m a x = V o u t _ m a x 30 = 1.5 V
Equation 45. V A T R K _ m i n = V o u t _ m i n 30 = 0.4 V

The output voltage can also be programmed by digital PWM signal (DTRK). The duty cycle DTRK can be found as:

Equation 46. D T R K = V o u t _ m a x 0.75 V × 10 0 % = 60 %
Equation 47. D T R K _ m i n = V o u t _ m i n 0.75 V × 10 0 % = 16 %

Make sure the DTRK frequency is between 100kHz and 2200kHz.

A two stage RC filter with offset can be utilized to convert a digital PWM signal to analog voltage as shown in Figure 7-5.

The two stage RC filter is used to filter the PWM signal into a smooth analog voltage. The two stage RC filter is selected considering voltage ripple and rise time on ATRK/DTRK.

Pullup resistor (RPU) and pulldown resistor (RPD) are utilized to add an offset voltage to ATRK/DTRK so that 100% PWM duty cycle sets the output voltage to Vout_max and 0% PWM duty cycle sets the output voltage to Vout_min.

LM5125-Q1 Two Stage RC Filter to ATRK/DTRK Figure 7-5 Two Stage RC Filter to ATRK/DTRK

In this application, 400kHz PWM frequency is used. Rf=4.99kΩ, Cf=47nF are selected for the filter. Ra=1.5kΩ, RPU=51kΩ, RPD=7.87kΩ are selected to create a proper offset voltage.

The voltage ripple and rise time of ATRK/DTRK can be observed in Figure 7-6 and Figure 7-7. The voltage ripple at ATRK/DTRK is 9.2μV, which is pretty low. And rise time of around 1ms is also good for the audio system.

LM5125-Q1 Voltage Ripple of ATRK/DTRK Figure 7-6 Voltage Ripple of ATRK/DTRK
LM5125-Q1 Rise Time of ATRK/DTRK Figure 7-7 Rise Time of ATRK/DTRK