SNVSC77 December   2024 LM5125-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Device Configuration (CFG0-pin, CFG1-pin, CFG2-pin)
      2. 6.3.2  Switching Frequency and Synchronization (SYNCIN)
      3. 6.3.3  Dual Random Spread Spectrum (DRSS)
      4. 6.3.4  Operation Modes (BYPASS, DEM, FPWM)
      5. 6.3.5  Dual- and Multi-phase Operation
      6. 6.3.6  BIAS (BIAS-pin)
      7. 6.3.7  Soft Start (SS-pin)
      8. 6.3.8  VOUT Programming (VOUT, ATRK, DTRK)
      9. 6.3.9  Protections
      10. 6.3.10 VOUT Overvoltage Protection (OVP)
      11. 6.3.11 Thermal Shutdown (TSD)
      12. 6.3.12 Power-Good Indicator (PGOOD-pin)
      13. 6.3.13 Current Sensing, Peak Current Limit, and Slope Compensation (CSP1, CSP2, CSN1, CSN2)
      14. 6.3.14 Current Sense Programming (CSP1, CSP2, CSN1, CSN2)
      15. 6.3.15 Input Current Limit and Monitoring (ILIM, IMON, DLY)
      16. 6.3.16 Signal Deglitch Overview
      17. 6.3.17 MOSFET Drivers, Integrated Boot Diode, and Hiccup Mode Fault Protection (LOx, HOx, HBx-pin)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown State
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Feedback Compensation
    2. 7.2 Typical Application
      1. 7.2.1 Application
      2. 7.2.2 Design Requirements
      3. 7.2.3 Detailed Design Procedure
        1. 7.2.3.1  Determine the Total Phase Number
        2. 7.2.3.2  Determining the Duty Cycle
        3. 7.2.3.3  Timing Resistor RT
        4. 7.2.3.4  Inductor Selection Lm
        5. 7.2.3.5  Current Sense Resistor Rcs
        6. 7.2.3.6  Current Sense Filter RCSFP, RCSFN, CCS
        7. 7.2.3.7  Low-Side Power Switch QL
        8. 7.2.3.8  High-Side Power Switch QH and Additional Parallel Schottky Diode
        9. 7.2.3.9  Snubber Components
        10. 7.2.3.10 Vout Programming
        11. 7.2.3.11 Input Current Limit (ILIM/IMON)
        12. 7.2.3.12 UVLO Divider
        13. 7.2.3.13 Soft Start
        14. 7.2.3.14 CFG Settings
        15. 7.2.3.15 Output Capacitor Cout
        16. 7.2.3.16 Input Capacitor Cin
        17. 7.2.3.17 Bootstrap Capacitor
        18. 7.2.3.18 VCC Capacitor CVCC
        19. 7.2.3.19 BIAS Capacitor
        20. 7.2.3.20 VOUT Capacitor
        21. 7.2.3.21 Loop Compensation
      4. 7.2.4 Application Curves
        1. 7.2.4.1 Efficiency
        2. 7.2.4.2 Steady State Waveforms
        3. 7.2.4.3 Step Load Response
        4. 7.2.4.4 Sync Operation
        5. 7.2.4.5 Thermal Performance
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Tape and Reel Information
    2.     85

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)

6.3.17 MOSFET Drivers, Integrated Boot Diode, and Hiccup Mode Fault Protection (LOx, HOx, HBx-pin)

The device integrates N-channel logic MOSFET drivers. The LOx driver is powered by VCC and the HOx driver is powered by HBx. When the SWx-pin voltage is approximately 0V by turning on the low-side MOSFET, the capacitor CHBx is charged from VCC through the internal boot diode. The recommended value of CHBx is 0.1μF. During shutdown, the gate drivers outputs are high impedance.

The LOx and HOx outputs are controlled with an adaptive dead-time methodology, which makes sure that both outputs are not turned on at the same time to prevent shoot through. When the device turns on LOx the adaptive dead-time logic turns off HOx and waits for the HOx-SWx voltage to drop below typically 1.5V, then LOx is turned on after a small dead-time delay tDHL. Also the HOx driver turn-on is delayed until the LOx-PGND voltage has discharged below typically 1.5V. HOx is then turned on after a small dead-time delay tDLH.

If the driver output voltage is lower than the MOSFET gate plateau voltage during start-up, the converter can not start up properly and can be stuck at the maximum duty cycle in a high-power dissipation state. This condition can be avoided by selecting a lower threshold MOSFET or by turning on the device when the BIAS-pin voltage is sufficient. During bypass operation the minimum HOx-SWx voltage is 3.75V.

The hiccup mode fault protection is triggered by HBx-UVLO. If the HBx-SWx voltage is less than the HBx UVLO threshold (VHB-UVLO), LOx turns on by force for 75ns to replenish the boost capacitor. The device allows up to four consecutive replenish switching. After the maximum four consecutive boot replenish switching, the device skips switching for 12 cycles. If the device fails to replenish the boost capacitor after the four sets of the four consecutive replenish switching, the device stops switching and enters 512 cycles of hiccup mode off-time. During the hiccup mode off-time PGOOD = low and the SS-pin is grounded.

If required the slew rate of the switching node voltage can be adjusted by adding a gate resistor in parallel with pulldown PNP transistor. The resistor can decrease the effective dead-time.

LM5125-Q1 Slew Rate Control Figure 6-21 Slew Rate Control