SNVSC77 December   2024 LM5125-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Device Configuration (CFG0-pin, CFG1-pin, CFG2-pin)
      2. 6.3.2  Switching Frequency and Synchronization (SYNCIN)
      3. 6.3.3  Dual Random Spread Spectrum (DRSS)
      4. 6.3.4  Operation Modes (BYPASS, DEM, FPWM)
      5. 6.3.5  Dual- and Multi-phase Operation
      6. 6.3.6  BIAS (BIAS-pin)
      7. 6.3.7  Soft Start (SS-pin)
      8. 6.3.8  VOUT Programming (VOUT, ATRK, DTRK)
      9. 6.3.9  Protections
      10. 6.3.10 VOUT Overvoltage Protection (OVP)
      11. 6.3.11 Thermal Shutdown (TSD)
      12. 6.3.12 Power-Good Indicator (PGOOD-pin)
      13. 6.3.13 Current Sensing, Peak Current Limit, and Slope Compensation (CSP1, CSP2, CSN1, CSN2)
      14. 6.3.14 Current Sense Programming (CSP1, CSP2, CSN1, CSN2)
      15. 6.3.15 Input Current Limit and Monitoring (ILIM, IMON, DLY)
      16. 6.3.16 Signal Deglitch Overview
      17. 6.3.17 MOSFET Drivers, Integrated Boot Diode, and Hiccup Mode Fault Protection (LOx, HOx, HBx-pin)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown State
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Feedback Compensation
    2. 7.2 Typical Application
      1. 7.2.1 Application
      2. 7.2.2 Design Requirements
      3. 7.2.3 Detailed Design Procedure
        1. 7.2.3.1  Determine the Total Phase Number
        2. 7.2.3.2  Determining the Duty Cycle
        3. 7.2.3.3  Timing Resistor RT
        4. 7.2.3.4  Inductor Selection Lm
        5. 7.2.3.5  Current Sense Resistor Rcs
        6. 7.2.3.6  Current Sense Filter RCSFP, RCSFN, CCS
        7. 7.2.3.7  Low-Side Power Switch QL
        8. 7.2.3.8  High-Side Power Switch QH and Additional Parallel Schottky Diode
        9. 7.2.3.9  Snubber Components
        10. 7.2.3.10 Vout Programming
        11. 7.2.3.11 Input Current Limit (ILIM/IMON)
        12. 7.2.3.12 UVLO Divider
        13. 7.2.3.13 Soft Start
        14. 7.2.3.14 CFG Settings
        15. 7.2.3.15 Output Capacitor Cout
        16. 7.2.3.16 Input Capacitor Cin
        17. 7.2.3.17 Bootstrap Capacitor
        18. 7.2.3.18 VCC Capacitor CVCC
        19. 7.2.3.19 BIAS Capacitor
        20. 7.2.3.20 VOUT Capacitor
        21. 7.2.3.21 Loop Compensation
      4. 7.2.4 Application Curves
        1. 7.2.4.1 Efficiency
        2. 7.2.4.2 Steady State Waveforms
        3. 7.2.4.3 Step Load Response
        4. 7.2.4.4 Sync Operation
        5. 7.2.4.5 Thermal Performance
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Tape and Reel Information
    2.     85

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)

7.4.1 Layout Guidelines

The performance of switching converters heavily depends on the quality of the PCB layout. Poor PCB design can cause among others converter instability, load regulation problems, noise or EMI issues. Thermal relieved connections in the power path, for VCC or the bootstrap capacitor, must not be used as thermal relieved connections add significant inductance.

  • Place the VCC, BIAS, HB1 and HB2 capacitors close to the corresponding device pins and connect them with short and wide traces to minimize inductance, as the capacitors carry high peak currents.
  • Place CSN1, CSP1, CSN2, and CSP2 filter resistors and capacitors close to the corresponding device pins to minimize noise coupling between the filter and the device. Route the traces to the sense resistors RCS1 and RCS2, which are placed close to the inductor, as differential pair and surrounded by ground to avoid noise coupling. Use Kelvin connections to the sense resistors.
  • Place the compensation network RCOMP and CCOMP as well as the frequency setting resistor RRT close to the corresponding device pins and connect them with short traces to avoid noise coupling. Connect the analog ground pin AGND to these components.
  • Place the ATRK resistor RATRK (when used) close to the ATRK pin and connect to AGND.
  • Note the layout of following components is not so critical:
    • Soft-start capacitor CSS
    • DLY capacitor CDLY
    • ILIM/IMON resistor and capacitor RILIM and CILIM
    • CFG0, CFG1 and CFG2 resistors
    • UVLO/EN resistors
  • Connect the AGND and PGND pin directly to the exposed pad (EP) to form a star connection at the device.
  • Connect the device exposed pad (EP) with several vias to a ground plane to conduct heat away.
  • Separate power and signal traces and use a ground plane to provide noise shielding.

The gate drivers incorporate short propagation delays, automatic dead time control, and low-impedance output stages capable of delivering high peak currents. Fast rise, fall times emake sure of rapid turn-on and turn-off transitions of the power MOSFETs enabling high efficiency. Stray and parasitic gate loop inductance must be minimized to avoid high ringing.

  • Place the high-side and low-side MOSFETs close to the device.
  • Connect the gate driver outputs HO1, HO2, LO1 and LO2 with a short trace to minimize inductance.
  • Route HO1, HO2 and SW1, SW2 to the MOSFETs as a differential pair using the flux cancellation effect reducing the loop area.
  • Place the VOUT capacitors close to the high-side MOSFETs. Use short and wide traces to minimize the power stage loop COUT to high-side MOSFET drain connection to avoid high voltage spikes at the MOSFET.
  • Connect the low-side MOSFET source connection with short and wide traces to the VOUT and VI capacitors ground to minimize inductance causing high voltage spikes at the MOSFET.
  • Use copper areas for cooling at the MOSFETs thermal pads.

To spread the heat generated by the MOSFETs and the inductor, place the inductor away from the power stage (MOSFETs). However, the longer the trace between the inductor and the low-side MOSFET (switch node) the higher the EMI and noise emissions. For highest efficiency, connect the inductor by wide and short traces to minimize resistive losses.