The LM5137-Q1 high-side and low-side gate drivers incorporate short propagation delays, adaptive deadtime control, and low-impedance output stages capable of delivering large peak currents with very fast rise and fall times to facilitate rapid turn-on and turnoff transitions of the power MOSFETs. Very high di/dt can cause unacceptable ringing if the trace lengths and impedances are not well controlled.

Minimization of stray or parasitic gate loop inductance is key to optimizing gate drive switching performance, whether it be series gate inductance that resonates with MOSFET gate capacitance or common source inductance (common to gate and power loops) that provides a negative feedback component opposing the gate drive command, thereby increasing MOSFET switching times. The following loops are important:

• Loop 2: high-side MOSFET, Q₁. During the high-side MOSFET turn-on, high current flows from the bootstrap (boot) capacitor through the gate driver and high-side MOSFET, and back to the negative terminal of the boot capacitor through the SW connection. Conversely, to turn off the high-side MOSFET, high current flows from the gate of the high-side MOSFET through the gate driver and SW, and back to the source of the high-side MOSFET through the SW trace. Refer to "loop 2" of Figure 8-25.
• Loop 3: low-side MOSFET, Q₂. During the low-side MOSFET turn-on, high current flows from the VCC decoupling capacitor through the gate driver and low-side MOSFET, and back to the negative terminal of the capacitor through ground. Conversely, to turn off the low-side MOSFET, high current flows from the gate of the low-side MOSFET through the gate driver and GND, and back to the source of the low-side MOSFET through ground. Refer to "loop 3" of Figure 8-25.

TI strongly recommends following circuit layout guidelines when designing with high-speed MOSFET gate drive circuits.

• Connections from gate driver outputs, HO1/HO2 and LO1/LO2, to the respective gates of the high-side or low-side MOSFETs must be as short as possible to reduce series parasitic inductance. Be aware that peak gate drive currents can be as high as 3A. Use 0.65mm (25mils) or wider traces. Use via or vias, if necessary, of at least 0.5mm (20mils) diameter along these traces. Route the [HO1, SW1] and [HO2, SW2] gate traces as differential pairs from the LM5137-Q1 to the applicable high-side MOSFETs, taking advantage of flux cancellation.
• Minimize the current loop path from the VCC and CBOOT1/CBOOT2 pins through the respective capacitors as these provide the high instantaneous current, up to 3A, to charge the MOSFET gate capacitances. Specifically, locate the bootstrap capacitors, C_BST1 and C_BST2, close to the respective [CBOOT1, SW1] and [CBOOT2, SW2] pin pairs of the LM5137-Q1 to minimize the areas of "loop 2" associated with the high-side drivers. Similarly, locate the VCC capacitor, C_VCC, close to the VCC and PGND pins of the LM5137-Q1 to minimize the areas of "loop 3" associated with the low-side drivers.