Table 1. Design Parameters

8.2.2.1 Inductor Calculation

For peak current mode control, sub-harmonic oscillation occurs with a duty cycle greater than 50% and is characterized by alternating wide and narrow pulses at the SW pin. By adding a slope compensating ramp equal to at least one-half the inductor current down-slope, any tendency toward sub-harmonic oscillation is damped within one switching cycle. For design simplification, the LM5140-Q1 has an internal slope compensation ramp added to the current sense signal.

For the slope compensation ramp to dampen sub-harmonic oscillation, the inductor value should be calculated based on the following guidelines (Equation 14 assumes an inductor ripple current 30%):

Equation 14.

• Lower inductor values increase the peak-to-peak inductor current, which minimizes size and cost and improves transient response at the expense of reduced efficiency due to higher peak currents.
• Higher inductance values decrease the peak-to-peak inductor current, which increases efficiency by reducing the RMS current but requires larger output capacitors to meet load-transient specifications.

Equation 15.

A standard inductor value of 1.5 µH is selected.

Equation 16.

Equation 17.

The maximum peak-to-peak inductor current is calculated in Equation 18 through Equation 21:

Equation 18.

Equation 19.

Equation 20.

Equation 21.

8.2.2.2 Current Sense Resistor

When calculating the current sense resistor, the maximum output current capability (IOUT_MAX) must be at least 20% higher than the required full load current to account for tolerances, ripple current, and load transients. For this example, 120% of the 6.41-A peak inductor current calculated in the previous section (Ipk) is 7.69 A. The current sense resistor value can be calculated using Equation 22 and Equation 23:

Equation 22.

Equation 23.

where

• V_CS is the 73 mV current limit threshold.

The Rsense value selected is 9 mΩ

Carefully observe the PCB layout guidelines to ensure that noise and DC errors do not corrupt the differential current sense signals between the CS and VOUT pins. Place the sense resistor close to the devices with short, direct traces, creating Kelvin-sense connections between the current-sense resistor and the LM5140-Q1.

The propagation delays through the current limit comparator, logic, and external MOSFET gate drivers allow the peak current to increase above the calculated current limit threshold. For a total propogation delay of t_dlyTOTAL, the worst case peak current through the inductor with the output is shorted can be calculated from Equation 24:

Equation 24.

From the Electrical Characteristics, t_dlyTOTAL 40 ns (see Equation 25)

Equation 25.

Once the peak current and the inductance parameters are known, the inductor can be chosen. An inductor with a saturation current greater than Ipk_shortckt (8.59 Apk) should be selected.

8.2.2.3 Output Capacitor

In a switch mode power supply, the minimum output capacitance is typically selected based on the capacitor ripple current rating and the load transient requirements. The output capacitor must be large enough to absorb the inductor energy and limit over voltage when transitioning from full-load to no-load, and to limit the output voltage undershoot during no-load to full load transients. The worst-case load transient from zero to full load occurs when the input voltage is at the maximum value and a current switching cycle has just finished. The total output voltage drop VOUT_UV is the sum of the voltage drop while the inductor is ramping up to support the full load and the voltage drop before the next pulse can occur.

The output capacitance required to maintain the minimum output voltage drop VOUT_UV can be calculated in Equation 26 and Equation 27:

Equation 26.

Equation 27.

where

• I_STEP = 6 A
• VOUT_UV = 1% of 3.3 V, or 33 mV

For this example a total of 293 µF of capacitance is used, three 82-µF aluminum capacitors for energy storage and one 47-µF low ESR ceramic capacitor to reduce high frequency noise.

Generally, when sufficient capacitance is used to satisfy the undershoot requirement, the overshoot during a full-load to no-load transient will also be satisfactory. After the output capacitance has been selected, calculate the output ripple current and verify that the ripple current is within the capacitor ripple current ratings.

For this design, the output ripple current is calculated in Equation 28 and Equation 29:

Equation 28.

Equation 29.

8.2.2.4 Input Filter

A power supply input typically has a relatively high source impedance at the switching frequency. Good-quality input capacitors are necessary to limit the ripple voltage at the VIN pin while supplying most of the switch current during the buck switch on-time. When the buck switch turns on, the current drawn from the input capacitor steps from zero to the valley of the inductor current waveform, then ramps up to the peak value, and then drops to the zero at turnoff.

Average input current can be calculated from the total input power required to support the loads at VOUT1 and VOUT2 in Equation 30:

Equation 30.

The efficiency η is assumed to be 83% for this design example, yielding total input power:

Equation 31.

Equation 32.

Equation 33.

The ripple voltage on the input capacitors is reduced significantly with a dual-channel operation because each channel operates 180º out of phase from the other. Capacitors connected in parallel should be evaluated for their RMS current rating. The ripple current splits between the input capacitors based on the relative impedance of the capacitors at the switching frequency.

The input capacitors must be selected with sufficient RMS current rating and the maximum voltage rating. The input ripple current with one channel operating is calculated in Equation 34 and Equation 35:

Equation 34.

Equation 35.

8.2.2.5 EMI Filter Design

Switching regulators exhibit negative input impedance, which is lowest at the minimum input voltage. An under-damped LC filter exhibits a high output impedance at the resonant frequency of the filter. For stability, the filter output impedance must be less than the absolute value of the converter input impedance.

Equation 36.

Equation 37.

EMI Filter Design Steps:

• Calculate the required attenuation
• Capacitor C_IN represents the existing capacitor at the input of the switching converter
• Filter inductor L_f is usually selected between 1 μH and 10 μH (3.6 µH was used for this application), but it can be smaller to reduce losses in a high current design
• Calculate capacitor C_f

Figure 32. Input EMI Filter

By calculating the first harmonic current from the Fourier series of the input current waveform and multiplying it by the input impedance (the impedance is defined by the existing input capacitor C_IN), a formula can be derived to obtain the required attenuation (see Equation 38 and Equation 39):

Equation 38.

Equation 39.

Vmax is the allowed dBμV noise level for the particular EMI standard, C_IN is the existing input capacitors of the buck converter. For this application 10 µF was selected. Dmax is the maximum duty cycle. I_pk is the peak inductor current and for filter design purposes, the current at the input can be modeled as a squarewave. The EMI filter capacitor C_f is determined from:

Equation 40.

Equation 41.

For this application, C_f was chosen to be 1 µF. Adding an input filter to a switching regulator modifies the control-to-output transfer function. The output impedance of the filter must be sufficiently small such that the input filter does not significantly affect the loop gain of the buck converter. The impedance peaks at the filter resonant frequency. The resonant frequency of the filter is given by Equation 42 and Equation 43:

Equation 42.

Equation 43.

The purpose of R_d is to reduce the peak output impedance of the filter at the resonant frequency. The capacitor C_d blocks the DC component of the input voltage to avoids excessive power dissipation in R_d. The capacitor C_d must have lower impedance than R_d at the resonant frequency with a capacitance value greater than the input capacitor C_IN. This prevents the C_IN from interfering with the cutoff frequency of the main filter. Added damping is needed when the output impedance is high at the resonant frequency ( Q of filter formed by C_IN and L_f is too high): An electrolytic cap C_d can be used as damping device, with the value of Equation 44:

Equation 44.

C_d = 4 × 10 µF, a 47-µF capacitor was selected and R_d is chosen using Equation 45 and Equation 46:

Equation 45.

Equation 46.

8.2.2.6 MOSFET Selection

The LM5140-Q1 gate drivers are powered by the internal 5-V VCC bias regulator. To reduce power dissipation in the controller and improve efficiency, the VCCX pin which must be connected to 5-V output or an external 5-V bias supply. The MOSFETs used with the LM5140 require a logic-level gate threshold with on-resistance specified with V_GS = 4.5 V or lower.

The four MOSFETs must be chosen with a V_DS rating to withstand the maximum V_IN voltage plus supply voltage transients and spikes (ringing). For automotive applications, the maximum V_IN occurs during a load dump and the voltage can surge to 42 V under some conditions. A MOSFET with a V_DS rating of 60 V would meet most application requirements. The N-channel MOSFETs must be capable of delivering the average load current plus peak ripple current during switching.

The high-side MOSFET losses are associated with the R_DS(ON) of the MOSFET and the switching losses.

Equation 47.

Equation 48.

The losses in the low-side MOSFET include the R_DS(ON) losses, the dead time losses, and losses in the MOSFETs internal body diode. The body diode conducts the inductor current during the dead time before the rising edge of the switch node. Minority carriers are injected into and stored in the body diode PN junction. As the high-side FET begins to turn on, a negative current must first flow through the diode to remove the stored charge before the diode can be reverse biased. During this time, the high-side MOSFET drain-source voltage remains at V_IN until all the diode minority carriers are removed. Then the diode begins to block negative voltage and the reverse current continues to flow to charge the depletion capacitance of the body diode junction. The total charge required to reverse bias the diode is called reverse-recovery charge Qrr. The power loss in the low-side MOSFET can be calculated from Equation 49 and Equation 50:

Equation 49.

Equation 50.

where

• t_dr and t_df are the switch node voltage rise and fall times (20 ns)
• V_DFET the forward voltage drop across the low-side MOSFET internal body diode (0.8 V)
• D_Qrr the internal body diode reverse recovery charge (105 nC)
• and R_DS(ON) the on resistance of the low-side MOSFET ( 26 mΩ at T_J = 125ºC)

Table 2 provides parameters for several MOSFETs that have tested in the LM5140-Q1 evaluation module.

8.2.2.7 Driver Slew Rate Control

Figure 33 shows the high current driver outputs with independent source and current sink pins for slew rate control. Slew rate control enables the user to adjust the switch node rise and fall times which can reduce the conducted EMI in the FM radio band (30 MHz to 108 MHz). Using the LM5140-Q1 EVM, conducted emission were measured in accordance with CISPR 25. Figure 34 shows the measured results without slew rate control. The conducted EMI results with slew rate control are shown in Figure 35.

Figure 33. Drivers With Slew Rate Control

Figure 34. EMI Measurements CISPR 25, No Slew Rate Control

Referring to Figure 34 and Figure 35 a 10-dB reduction in conduction emissions in the FM band is attained by using slew rate control. This can reduce the size and cost of the EMI filters.

Figure 35. EMI Measurements CISPR 25 With Slew Rate Control

8.2.2.8 Sub-Harmonic Oscillation

For peak current mode control, sub-harmonic oscillation occurs with a duty cycle greater than 50% and is characterized by alternating wide and narrow pulses at the SW pin. By adding a compensating ramp equal to the down-slope of the inductor current, any tendency toward sub-harmonic oscillation is damped within one switching cycle.

In time-domain analysis, the steady-state inductor current starts and ends at the same value during one clock cycle. If the magnitude of the end-of-cycle current error, dI₁, caused by an initial perturbation, dI₀, is less than the magnitude of dI₀ or dI₁/dI₀ > –1, the perturbation naturally disappears after a few cycles, refer to Figure 36. When dI₁/dI₀ < –1, the initial perturbation does not disappear resulting in sub-harmonic oscillation in steady-state operation. By choosing K > 1 , sub-harmonic oscillation is avoided.

Figure 36. Sub-Harmonic Oscillation

Equation 51.

The relationship between Q and K factor is illustrated graphically in Figure 37.

Figure 37. Sampling Gain Q vs K Factor

The minimum value of K is 0.5. This is the same as time domain analysis result. When K < 0.5, the regulator is unstable. High gain peaking at 0.5 results in sub-harmonic oscillation at F_SW//2. When K = 1, one-cycle damping is realized and Q is equal to 0.673 at this point. A higher K factor may introduce additional phase shift by moving the sampled gain inductor pole closer to the crossover frequency but helps reduce noise sensitivity in the current loop.

8.2.2.9 Control Loop

The open-loop gain is defined as the product of modulator and feedback transfer functions. When plotted on a dB scale, the open loop gain is shown as the sum of modulator gain and feedback gain.

DC modulator gain is calculated in Equation 52:

Equation 52.

where

• G_CS is the current sense amplifier gain (12)
• R_LOAD is the load resistance
• R_DCR is the dc resistance on the output inductor
• R_SENSE is the current sense resistance

The modulator gain plus power stage transfer function with an embedded current loop is shown in Equation 53. The equation included the sample gain at F_SW/2 (ωn), which is caused by sampling effect of current mode control.

Equation 53.

Equation 54.

Because the loop cross over frequency is well below sample gain effects, Equation 54 can be simplified as one pole and a one zero system as shown in Equation 55

Equation 55.

8.2.2.10 Error Amplifier

A type ll compensator using an transconductance error amplifier (EA) Gm is shown in Figure 38. The dominant pole of the EA open-loop gain is set by the EA output resistance, R_AMP, and effective bandwidth-limiting capacitance, C_O as follows:

Equation 56.

The EA high frequency pole is neglected in the above expression. The compensator transfer function from the output voltage to COMP, including the gain contribution from the feedback resistor divider network, is calculated in Equation 57:

Equation 57.

where

• V_REF is the feedback voltage reference (1.2 V)
• Gm is the error amplifier gain transconductance (1200 µS)
• and R_AMP is the error amplifier output impedance (2.5 MΩ)

Equation 58.

Equation 59.

Equation 60.

Equation 61.

Typically R_COMP <<R_AMP and C_COMP>> (C_O) so the approximations are valid.

Figure 38. Transconductance Amplifier

The error amplifier compensation components create a pole at the origin, a zero, and a high frequency pole.

The procedure for choosing compensation components for a stable closed loop is:

• Select the desired open-loop gain crossover frequency (fc); for this application 30 kHz was chosen
• Calculate the R_COMP resistor for the gain crossover frequency at 30 kHz
Equation 62.
Equation 63.

The value selected for R_COMP is 22.6 kΩ

• Calculate the C_COMP capacitor value to create a zero that cancels the pole ωp.

Equation 64.

Equation 65.

The value selected for C_COMP is 10 nF