SNVSA02A January   2016  – December 2016 LM5140-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  High Voltage Start-up Regulator
      2. 7.3.2  VCC Regulator
      3. 7.3.3  Oscillator
      4. 7.3.4  SYNIN and SYNOUT
      5. 7.3.5  Enable
      6. 7.3.6  Power Good
      7. 7.3.7  Output Voltage
      8. 7.3.8  Minimum Output Voltage Adjustment
      9. 7.3.9  Current Sense
      10. 7.3.10 DCR Current Sensing
      11. 7.3.11 Error Amplifier and PWM Comparator
      12. 7.3.12 Slope Compensation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Hiccup Mode Current Limiting
      2. 7.4.2 Standby Mode
      3. 7.4.3 Soft Start
      4. 7.4.4 Diode Emulation
      5. 7.4.5 High and low-side Drivers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Inductor Calculation
        2. 8.2.2.2  Current Sense Resistor
        3. 8.2.2.3  Output Capacitor
        4. 8.2.2.4  Input Filter
        5. 8.2.2.5  EMI Filter Design
        6. 8.2.2.6  MOSFET Selection
        7. 8.2.2.7  Driver Slew Rate Control
        8. 8.2.2.8  Sub-Harmonic Oscillation
        9. 8.2.2.9  Control Loop
        10. 8.2.2.10 Error Amplifier
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

Careful PCB layout is critical to achieve low EMI and stable power supply operation. If possible, mount all the power components on the top side of the board, making the high frequency current loops as small as possible, and follow these guidelines of good layout practices:

  1. Keep the high-current paths short. This practice is essential for stable, jitter-free operation.
  2. Keep the power traces and load connections short. This practice is essential for high efficiency. Using thick copper (2 oz) can enhance full load efficiency by 1% or more.
  3. Minimize current-sensing errors by routing CS and VOUT using a kelvin sensing directly across the current-sense resistor (Rsense).
  4. Route high-speed switching nodes (HB, HO, LO, and SW) away from sensitive analog areas (FB, CS, and VOUT).

10.1 Layout Guidelines

  • Place the power components first, with ground terminals adjacent to the low-side FET. If possible, make all these connections on the top layer with wide, copper-filled areas.
  • Mount the controller IC as close as possible to the high and low-side MOSFETs. Make the grounds and high and low-sided drive gate drive lines as short and wide as possible. Place the series gate drive resistor as close to the MOSFET as possible to minimize gate ringing.
  • Locate the gate drive components (D1 and C17) together and near the controller IC; refer to Figure 41. Be aware that peak gate drive currents can be as high as 4 A. Average current up to 150 mA can flow from the VCC pin to the VCC capacitor through the bootstrap diode to the bootstrap capacitor. Size the traces accordingly.
  • Make the ground connections to the LM5140-Q1 controller as shown in Figure 43. Create a power grounds directly connected to all high-power components and an analog ground plane for sensitive analog components. The analog ground plane (AGND) and power ground plane (PGND1, and PGND2) must be connected at a single point directly under the IC (at the die attach pad or DAP).
  • Figure 41 shows the schematic of the high frequency loops of one synchronous buck channel. The current flows through Q1 and Q2, through the power ground plane and back to VIN through the ceramic capacitors C11 and C12. This loop must be as small as possible to minimize EMI. See Figure 42 for the recommended PCB layout.

10.2 Layout Example

LM5140-Q1 synch_buck_power_snvsa02.png Figure 41. Synchronous Buck Power Flow
LM5140-Q1 sync_buck_high_freq_current_path_snvsa02.gif Figure 42. Synchronous Buck High Frequency Current Path
LM5140-Q1 AGND_and_PGND_conn_snvsa02.gif Figure 43. AGND and PGND Connections
LM5140-Q1 top_bottom_PWM_layers_snvsa02.gif Figure 44. Top and Bottom PWM Layers