SNVSC00A February   2023  – January 2025 LM5148-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Description (continued)
  6. 5 Pin Configuration and Functions
    1. 5.1 Wettable Flanks
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings 
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Voltage Range (VIN)
      2. 7.3.2  High-Voltage Bias Supply Regulator (VCC, VCCX, VDDA)
      3. 7.3.3  Precision Enable (EN)
      4. 7.3.4  Power-Good Monitor (PG)
      5. 7.3.5  Switching Frequency (RT)
      6. 7.3.6  Dual Random Spread Spectrum (DRSS)
      7. 7.3.7  Soft Start
      8. 7.3.8  Output Voltage Setpoint (FB)
      9. 7.3.9  Minimum Controllable On Time
      10. 7.3.10 Error Amplifier and PWM Comparator (FB, EXTCOMP)
      11. 7.3.11 Slope Compensation
      12. 7.3.12 Inductor Current Sense (ISNS+, VOUT)
        1. 7.3.12.1 Shunt Current Sensing
        2. 7.3.12.2 Inductor DCR Current Sensing
      13. 7.3.13 Hiccup Mode Current Limiting
      14. 7.3.14 High-Side and Low-Side Gate Drivers (HO, LO)
      15. 7.3.15 Output Configurations (CNFG)
      16. 7.3.16 Single-Output Dual-Phase Operation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Sleep Mode
      2. 7.4.2 Pulse Frequency Modulation and Synchronization (PFM/SYNC)
      3. 7.4.3 Thermal Shutdown
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Power Train Components
        1. 8.1.1.1 Buck Inductor
        2. 8.1.1.2 Output Capacitors
        3. 8.1.1.3 Input Capacitors
        4. 8.1.1.4 Power MOSFETs
        5. 8.1.1.5 EMI Filter
      2. 8.1.2 Error Amplifier and Compensation
    2. 8.2 Typical Applications
      1. 8.2.1 Design 1 – High Efficiency 2.1MHz Synchronous Buck Regulator
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Custom Design with WEBENCH® Tools
          2. 8.2.1.2.2 Custom Design with Excel Quickstart Tool
          3. 8.2.1.2.3 Buck Inductor
          4. 8.2.1.2.4 Current-Sense Resistance
          5. 8.2.1.2.5 Output Capacitors
          6. 8.2.1.2.6 Input Capacitors
          7. 8.2.1.2.7 Frequency Set Resistor
          8. 8.2.1.2.8 Feedback Resistors
          9. 8.2.1.2.9 Compensation Components
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Design 2 – High Efficiency 48-V to 12-V 400-kHz Synchronous Buck Regulator
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
      3. 8.2.3 Design 3 – High Efficiency 440-kHz Synchronous Buck Regulator
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
        3. 8.2.3.3 Application Curves
      4. 8.2.4 Design 4 – Dual-Phase 400-kHz 20-A Synchronous Buck Regulator
        1. 8.2.4.1 Design Requirements
        2. 8.2.4.2 Detailed Design Procedure
        3. 8.2.4.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Power Stage Layout
        2. 8.4.1.2 Gate-Drive Layout
        3. 8.4.1.3 PWM Controller Layout
        4. 8.4.1.4 Thermal Design and Layout
        5. 8.4.1.5 Ground Plane Design
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 Custom Design with WEBENCH® Tools
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
        1. 9.2.1.1 PCB Layout Resources
        2. 9.2.1.2 Thermal Design Resources
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.1 Wettable Flanks

100% automated visual inspection (AVI) post-assembly is typically required to meet reliability and robustness standards. Standard quad-flat no-lead (QFN) packages do not have solderable or exposed pins and terminals that are easily viewed. Visually determining whether or not the package is successfully soldered onto the printed-circuit board (PCB) is difficult. The wettable-flank process was developed to resolve the issue of side-lead wetting of leadless packaging. The LM5148-Q1 is assembled using a 24-pin VQFN and a 19-pin VQFN package with wettable flanks to provide a visual indicator of solderability, which reduces the inspection time and manufacturing costs1.