SNVSC01 February   2023 LM5148

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Input Voltage Range (VIN)
      2. 8.3.2  High-Voltage Bias Supply Regulator (VCC, VCCX, VDDA)
      3. 8.3.3  Precision Enable (EN)
      4. 8.3.4  Power-Good Monitor (PG)
      5. 8.3.5  Switching Frequency (RT)
      6. 8.3.6  Dual Random Spread Spectrum (DRSS)
      7. 8.3.7  Soft Start
      8. 8.3.8  Output Voltage Setpoint (FB)
      9. 8.3.9  Minimum Controllable On Time
      10. 8.3.10 Error Amplifier and PWM Comparator (FB, EXTCOMP)
      11. 8.3.11 Slope Compensation
      12. 8.3.12 Inductor Current Sense (ISNS+, VOUT)
        1. 8.3.12.1 Shunt Current Sensing
        2. 8.3.12.2 Inductor DCR Current Sensing
      13. 8.3.13 Hiccup Mode Current Limiting
      14. 8.3.14 High-Side and Low-Side Gate Drivers (HO, LO)
      15. 8.3.15 Output Configurations (CNFG)
      16. 8.3.16 Single-Output Dual-Phase Operation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Sleep Mode
      2. 8.4.2 Pulse Frequency Modulation and Synchronization (PFM/SYNC)
      3. 8.4.3 Thermal Shutdown
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Power Train Components
        1. 9.1.1.1 Buck Inductor
        2. 9.1.1.2 Output Capacitors
        3. 9.1.1.3 Input Capacitors
        4. 9.1.1.4 Power MOSFETs
        5. 9.1.1.5 EMI Filter
      2. 9.1.2 Error Amplifier and Compensation
    2. 9.2 Typical Applications
      1. 9.2.1 Design 1 – High Efficiency 2.1-MHz Synchronous Buck Regulator
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Custom Design with WEBENCH® Tools
          2. 9.2.1.2.2 Custom Design with Excel Quickstart Tool
          3. 9.2.1.2.3 Buck Inductor
          4. 9.2.1.2.4 Current-Sense Resistance
          5. 9.2.1.2.5 Output Capacitors
          6. 9.2.1.2.6 Input Capacitors
          7. 9.2.1.2.7 Frequency Set Resistor
          8. 9.2.1.2.8 Feedback Resistors
          9. 9.2.1.2.9 Compensation Components
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Design 2 – High Efficiency 48-V to 12-V 400-kHz Synchronous Buck Regulator
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Design 3 – High Efficiency 440-kHz Synchronous Buck Regulator
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curves
      4. 9.2.4 Design 4 – Dual-Phase 400-kHz 20-A Synchronous Buck Regulator
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
        3. 9.2.4.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Power Stage Layout
        2. 9.4.1.2 Gate-Drive Layout
        3. 9.4.1.3 PWM Controller Layout
        4. 9.4.1.4 Thermal Design and Layout
        5. 9.4.1.5 Ground Plane Design
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
        1. 10.1.1.1 Custom Design with WEBENCH® Tools
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
        1. 10.2.1.1 PCB Layout Resources
        2. 10.2.1.2 Thermal Design Resources
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.4.1.2 Gate-Drive Layout

The LM25148-Q1 high-side and low-side gate drivers incorporate short propagation delays, adaptive dead-time control, and low-impedance output stages capable of delivering large peak currents with very fast rise and fall times to facilitate rapid turn-on and turn-off transitions of the power MOSFETs. Very high di/dt can cause unacceptable ringing if the trace lengths and impedances are not well controlled.

Minimization of stray or parasitic gate loop inductance is key to optimizing gate drive switching performance, whether it be series gate inductance that resonates with MOSFET gate capacitance or common source inductance (common to gate and power loops) that provides a negative feedback component opposing the gate drive command, thereby increasing MOSFET switching times. The following loops are important:

  • Loop 2: high-side MOSFET, Q1. During the high-side MOSFET turnon, high current flows from the bootstrap (boot) capacitor through the gate driver and high-side MOSFET, and back to the negative terminal of the boot capacitor through the SW connection. Conversely, to turn off the high-side MOSFET, high current flows from the gate of the high-side MOSFET through the gate driver and SW, and back to the source of the high-side MOSFET through the SW trace. Refer to loop 2 of GUID-6CFB9914-50AB-4847-9B74-DE78EA03AA6F.html#SNVSAI48000.
  • Loop 3: low-side MOSFET, Q2. During the low-side MOSFET turnon, high current flows from the VCC decoupling capacitor through the gate driver and low-side MOSFET, and back to the negative terminal of the capacitor through ground. Conversely, to turn off the low-side MOSFET, high current flows from the gate of the low-side MOSFET through the gate driver and GND, and back to the source of the low-side MOSFET through ground. Refer to loop 3 of GUID-6CFB9914-50AB-4847-9B74-DE78EA03AA6F.html#SNVSAI48000.

TI strongly recommends following circuit layout guidelines when designing with high-speed MOSFET gate drive circuits.

  • Connections from gate driver outputs, HO and LO, to the respective gates of the high-side or low-side MOSFETs must be as short as possible to reduce series parasitic inductance. Be aware that peak gate drive currents can be as high as 3.3 A. Use 0.65 mm (25 mils) or wider traces. Use via or vias, if necessary, of at least 0.5 mm (20 mils) diameter along these traces. Route HO and SW gate traces as a differential pair from the LM5148 to the high-side MOSFET, taking advantage of flux cancellation.
  • Minimize the current loop path from the VCC and HB pins through their respective capacitors as these provide the high instantaneous current, up to 3.3 A, to charge the MOSFET gate capacitances. Specifically, locate the bootstrap capacitor, CBST, close to the CBOOT and SW pins of the LM25148-Q1 to minimize the area of loop 2 associated with the high-side driver. Similarly, locate the VCC capacitor, CVCC, close to the VCC and PGND pins of the LM5148 to minimize the area of loop 3 associated with the low-side driver.