SNVSAP6C September 2017 – October 2021 LM5150-Q1
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
SUPPLY CURRENT | ||||||
ISHUTDOWN(VOUT) | VOUT shutdown current | VVOUT = 12 V, VEN = 0 V | 5 | 12 | µA | |
ISTANDBY(VOUT) | VOUT standby current (PVCC in regulation, STATUS is low) | VVOUT = 12 V, VEN = 3.3 V, RSET = 90.9 kΩ | 15 | 25 | µA | |
IWAKEUP(VOUT) | VOUT operating current (exclude current into RT resistor) | VVOUT = 10.5 V, VEN = 2.5 V, non-switching, RT = 9.09 kΩ | 1.2 | 2.0 | mA | |
ISHUTDOWN(VIN) | VIN shutdown current | VVIN = 12 V, VEN = 0 V | 0.1 | 0.5 | µA | |
ISTANDBY(VIN) | VIN standby current | VVIN = 12 V, VEN = 3.3 V, RSET = 29.4 kΩ | 0.1 | 0.5 | µA | |
IWAKEUP(VIN) | VIN operating current | VVIN = 10.5 V, VEN = 2.5 V, non-switching, RT = 9.09 kΩ | 30 | 45 | µA | |
VCC REGULATOR | ||||||
VVCC-REG-NOLOAD | PVCC regulation | VVOUT = 6.0 V, No load, wake-up mode | 4.75 | 5 | 5.25 | V |
VVCC-REG-FULLLOAD | PVCC regulation | VVOUT = 5.0 V, IPVCC = 70 mA | 4.5 | 4.8 | V | |
VVCC-UVLO-RISING | AVCC UVLO threshold | AVCC rising | 4.1 | 4.3 | 4.5 | V |
VVCC-UVLO-FALLING | AVCC UVLO threshold | AVCC falling | 3.9 | 4.1 | 4.3 | V |
VVCC-UVLO-HYS | AVCC UVLO hysteresis | 0.2 | V | |||
IVCC-CL | PVCC sourcing current limit | VPVCC = 0 V, wake-up mode | 75 | mA | ||
ENABLE | ||||||
VEN-RISING | Enable threshold | EN rising | 1.7 | 2 | V | |
VEN-FALLING | Enable threshold | EN falling | 1 | 1.3 | V | |
IEN | EN bias current | VEN = 42 V | 100 | nA | ||
6.8-V SETTING | ||||||
VVOUT-REG | VOUT regulation target | RSET = 29.4 kΩ or 90.9 kΩ | 6.66 | 6.80 | 6.98 | V |
VVOUT-WAKEUP | VOUT wake-up threshold (VVOUT-REG + 3%) | RSET = 29.4 kΩ or 90.9 kΩ, VOUT falling | 6.83 | 7.00 | 7.14 | V |
VVOUT-STANDBY1 | VOUT standby threshold (VVOUT-REG + 6%, EC config) | RSET = 90.9 kΩ, VOUT rising | 7.02 | 7.21 | 7.35 | V |
VVOUT-STATUS-OFF | VOUT status off threshold (VVOUT-REG + 12%, EC config) | RSET = 90.9 kΩ, VOUT rising | 7.42 | 7.62 | 7.81 | V |
VVOUT-STANDBY2 | VOUT standby threshold (VVOUT-REG + 24%, SS config) | RSET = 29.4 kΩ, VOUT rising | 8.22 | 8.43 | 8.60 | V |
VVIN-STANDBY | VIN standby threshold (VVOUT-WAKEUP + 1.0 V, SS config) | RSET = 29.4 kΩ, VIN rising | 7.82 | 8.00 | 8.19 | V |
7.5-V SETTING | ||||||
VVOUT-REG | VOUT regulation target | RSET = 19.1 kΩ or 71.5 kΩ | 7.37 | 7.50 | 7.67 | V |
VVOUT-WAKEUP | VOUT wake-up threshold (VVOUT-REG + 3%) | RSET = 19.1 kΩ or 71.5 kΩ, VOUT falling | 7.52 | 7.73 | 7.88 | V |
VVOUT-STANDBY1 | VOUT standby threshold (VVOUT-REG + 6%, EC config) | RSET = 71.5 kΩ, VOUT rising | 7.74 | 7.95 | 8.11 | V |
VVOUT-STATUS-OFF | VOUT status off threshold (VVOUT-REG + 12%, EC config) | RSET = 71.5 kΩ, VOUT rising | 8.19 | 8.40 | 8.61 | V |
VVOUT-STANDBY2 | VOUT standby threshold (VVOUT-REG + 24%, SS config) | RSET = 19.1 kΩ, VOUT rising | 9.07 | 9.30 | 9.46 | V |
VVIN-STANDBY | VIN standby threshold (VVOUT-WAKEUP + 1.0 V, SS config) | RSET = 19.1 kΩ, VIN rising | 8.50 | 8.73 | 8.93 | V |
8.5-V SETTING | ||||||
VVOUT-REG | VOUT regulation target | RSET = 9.53 kΩ or 54.9 kΩ | 8.37 | 8.50 | 8.69 | V |
VVOUT-WAKEUP | VOUT wake-up threshold (VVOUT-REG + 3%) | RSET = 9.53 kΩ or 54.9 kΩ, VOUT falling | 8.52 | 8.76 | 8.93 | V |
VVOUT-STANDBY1 | VOUT standby threshold (VVOUT-REG + 6%, EC config) | RSET = 54.9 kΩ, VOUT rising | 8.78 | 9.01 | 9.19 | V |
VVOUT-STATUS-OFF | VOUT status off threshold (VVOUT-REG + 12%, EC config) | RSET = 54.9 kΩ, VOUT rising | 9.28 | 9.52 | 9.75 | V |
VVOUT-STANDBY2 | VOUT standby threshold (VVOUT-REG + 24%, SS config) | RSET = 9.53 kΩ, VOUT rising | 10.29 | 10.54 | 10.72 | V |
VVIN-STANDBY | VIN standby threshold (VVOUT-WAKEUP + 1.0 V, SS config) | RSET = 9.53 kΩ, VIN rising | 9.50 | 9.76 | 9.98 | V |
10.5-V SETTING | ||||||
VVOUT-REG | VOUT regulation target | RSET = GND or 41.2 kΩ | 10.31 | 10.50 | 10.75 | V |
VVOUT-WAKEUP | VOUT wake-up threshold (VVOUT-REG + 3%) | RSET = GND or 41.2 kΩ, VOUT falling | 10.53 | 10.82 | 11.02 | V |
VVOUT-STANDBY1 | VOUT standby threshold (VVOUT-REG + 6%, EC config) | RSET = 41.2 kΩ, VOUT rising | 10.84 | 11.13 | 11.33 | V |
VVOUT-STATUS-OFF | VOUT status off threshold (VVOUT-REG + 12%, EC config) | RSET = 41.2 kΩ, VOUT rising | 11.46 | 11.76 | 12.04 | V |
VVOUT-STANDBY2 | VOUT standby threshold (VVOUT-REG + 24%, SS config) | RSET = GND, VOUT rising | 12.70 | 13.02 | 13.24 | V |
VVIN-STANDBY | VIN standby threshold (VVOUT-WAKEUP + 1.0 V, SS config) | RSET = GND, VIN rising | 11.47 | 11.82 | 12.11 | V |
RT | ||||||
VRT-REG | RT regulation voltage | 1.2 | V | |||
CLOCK SYNCHRONIZATION | ||||||
VSYNC-RISING | SYNC rising threshold | 2.0 | 2.4 | V | ||
VSYNC-FALLING | SYNC falling threshold | 0.4 | 1.5 | V | ||
PULSE WIDTH MODULATION AND OSCILLATOR | ||||||
FSW1 | Switching frequency | RT = 93.1 kΩ | 204 | 239 | 270 | kHz |
FSW2 | Switching frequency | RT = 9.09 kΩ | 2100 | 2300 | 2500 | kHz |
FSW3 | Switching frequency | RT = 9.09 kΩ, FSYNC = 2.0 MHz | 2000 | kHz | ||
TON-MIN | Forced minimum on time | SS config, VCOMP = 0 V | 30 | 50 | 70 | ns |
DMIN | Minimum duty cycle limit (EC config) | RT = 9.09 kΩ, VVIN = 1.5 V, VVOUT = 6.8 V, VCOMP = 0 V | 60% | |||
RT = 93.1 kΩ, VVIN = 8.4 V, VVOUT = 10.5 V, VCOMP = 0 V | 16% | |||||
DMAX | Maximum duty cycle limit | SS config, RT = 9.09 kΩ | 83% | 87% | 91.5% | |
EC config, RT = 93.1 kΩ | 83% | 87% | 91.5% | |||
CURRENT SENSE | ||||||
VCSTH | Current limit threshold (CS-AGND)(1) | VVIN = 5.1 V, VVOUT = 6.8 V at 25% DC | 102 | 120 | 138 | mV |
VVIN = 3.4 V, VVOUT = 6.8 V at 50% DC | 102 | 120 | 138 | mV | ||
VVIN = 1.7 V, VVOUT = 6.8 V at 75% DC | 102 | 120 | 138 | mV | ||
ERROR AMPLIFIER | ||||||
Gm | Transconductance | 2 | mA/V | |||
COMP souring current | VCOMP = 0 V | 312 | µA | |||
COMP sinking current | VCOMP = 1.5 V | 120 | µA | |||
COMP clamp voltage | 2.4 | 2.6 | V | |||
COMP to PWM offset | 0.3 | V | ||||
STATUS | ||||||
Low-state voltage drop | 1-mA sinking | 0.1 | V | |||
STATUS rise to LO delay | 5-kΩ pullup to 5 V | 4 | 5 | 6 | µs | |
MOSFET DRIVER | ||||||
High-state voltage drop | 50-mA sinking | 0.075 | V | |||
Low-state voltage drop | 50-mA sourcing | 0.055 | V | |||
THERMAL SHUTDOWN (TSD) | ||||||
Thermal shutdown threshold | Temperature rising | 175 | °C | |||
Thermal shutdown hysteresis | 15 | °C |