SNVSAZ0C March 2018 – October 2021 LM51501-Q1
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
Based on the assumptions that 20% of current limit margin (MCL = 1.2), 80% estimated efficiency (Eff = 0.8) at full load and no RSL populated, RS is calculated using Equation 22 and Equation 23.
Substitute FSW_RT for FSYNC if clock synchronization is not used.
A standard value of 7 mΩ is chosen for RS. A low-ESL resistor is recommended to minimize the error caused by the ESL.