The LM5156x (LM5156 and LM51561) device is a wide input range, non-synchronous boost controller that uses peak current mode control. The device can be used in boost, SEPIC, and flyback topologies.
The LM5156x device can start up from a 1-cell battery with a minimum of 2.97 V if the BIAS pin is connected to the VCC pin. It can operate with the input supply voltage as low as 1.5 V if the BIAS pin is greater than 3.5 V.
PART NUMBER | PACKAGE(1) | BODY SIZE (NOM) |
---|---|---|
LM5156 | WSON (12) | 3.00 mm × 2.00 mm |
LM51561 |
DATE | REVISION | NOTES |
---|---|---|
January 2021 | * | Initial release. |
The internal VCC regulator also supports BIAS pin operation up to 60 V (65-V absolute maximum) . The switching frequency is dynamically programmable with an external resistor from 100 kHz to 2.2 MHz. Switching at 2.2 MHz minimizes AM band interference and allows for a small solution size and fast transient response. To reduce the EMI of the power supply, the device provides a selectable dual random spread spectrum which reduces the EMI over the wide frequency range.
The device features a 1.5-A standard MOSFET driver and a low 100-mV current limit threshold. The device also supports the use of an external VCC supply to improve efficiency. Low operating current and pulse-skipping operation improve efficiency at light loads.
The device has built-in protection features such as cycle-by-cycle current limit, overvoltage protection, line UVLO, and thermal shutdown. Hiccup mode overload protection is available in the LM51561 device option. Additional features include low shutdown IQ, programmable soft start, programmable slope compensation, precision reference, power-good indicator, and external clock synchronization.
DEVICE OPTION | HICCUP MODE PROTECTION | INTERNAL REFERENCE |
---|---|---|
LM5156 | Disabled | 1 V |
LM51561 | Enabled | 1 V |
PIN | TYPE(1) | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | BIAS | P | Supply voltage input to the VCC regulator. Connect a bypass capacitor from this pin to GND. |
2 | VCC | P | Output of the internal VCC regulator and supply voltage input of the MOSFET driver. Connect a ceramic bypass capacitor from this pin to GND. |
3 | GATE | O | N-channel MOSFET gate drive output. Connect directly to the gate of the N-channel MOSFET through a short, low inductance path. |
4 | GND | G | Ground pin. Connect directly to the ground connection of the sense resistor through a low inductance wide and short path. |
5 | CS | I | Current sense input pin. Connect to the positive side of the current sense resistor through a short path. |
6 | COMP | O | Output of the internal transconductance error amplifier. Connect the loop compensation components between this pin and GND. |
7 | DITHOFF | I | Spread spectrum selection pin. Internal spread spectrum (Clock dithering) is disabled when the pin is connected to the VCC pin. Connecting the pin to GND enables the internal spread spectrum. |
8 | FB | I | Inverting input of the error amplifier. Connect a voltage divider from the output to this pin to set output voltage in boost/SEPIC topologies. Connect the low-side feedback resistor to GND. |
9 | SS | I | Soft-start time programming pin. An external capacitor and an internal current source set the ramp rate of the internal error amplifier reference during soft start. Connect the ground connection of the capacitor to GND. |
10 | RT | I | Switching frequency setting pin. The switching frequency is programmed by a single resistor between RT and GND. |
11 | PGOOD | O | Power-good indicator. An open-drain output which goes low if FB is below the under voltage threshold. Connect a pullup resistor to the system voltage rail. |
12 | UVLO/SYNC/EN | I | Undervoltage lockout programming pin. The converter start-up and shutdown levels can be programmed by connecting this pin to the supply voltage through a resistor divider. The internal clock can be synchronized to an external clock by applying a negative pulse signal into the UVLO/SYNC/EN pin. This pin must not be left floating. Connect to BIAS pin if not used. Connect the low-side UVLO resistor to GND. |
— | EP | — | Exposed pad of the package. The exposed pad must be connected to GND and the large ground copper plane to decrease thermal resistance. |