SNVSBI7B January   2020  – January 2021 LM5156-Q1 , LM51561-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Line Undervoltage Lockout (UVLO/SYNC/EN Pin)
      2. 9.3.2  High Voltage VCC Regulator (BIAS, VCC Pin)
      3. 9.3.3  Soft Start (SS Pin)
      4. 9.3.4  Switching Frequency (RT Pin)
      5. 9.3.5  Dual Random Spread Spectrum (DRSS)
      6. 9.3.6  Clock Synchronization (UVLO/SYNC/EN Pin)
      7. 9.3.7  Current Sense and Slope Compensation (CS Pin)
      8. 9.3.8  Current Limit and Minimum On-time (CS Pin)
      9. 9.3.9  Feedback and Error Amplifier (FB, COMP Pin)
      10. 9.3.10 Power-Good Indicator (PGOOD pin)
      11. 9.3.11 Hiccup Mode Overload Protection (LM51561-Q1 Only)
      12. 9.3.12 Maximum Duty Cycle Limit and Minimum Input Supply Voltage
      13. 9.3.13 MOSFET Driver (GATE Pin)
      14. 9.3.14 Overvoltage Protection (OVP)
      15. 9.3.15 Thermal Shutdown (TSD)
    4. 9.4 Device Functional Modes
      1. 9.4.1 Shutdown Mode
      2. 9.4.2 Standby Mode
      3. 9.4.3 Run Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Custom Design With WEBENCH® Tools
        2. 10.2.2.2 Recommended Components
        3. 10.2.2.3 Inductor Selection (LM)
        4. 10.2.2.4 Output Capacitor (COUT)
        5. 10.2.2.5 Input Capacitor
        6. 10.2.2.6 MOSFET Selection
        7. 10.2.2.7 Diode Selection
        8. 10.2.2.8 Efficiency Estimation
      3. 10.2.3 Application Curve
    3. 10.3 System Examples
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Examples
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Development Support
        1. 13.1.1.1 Custom Design With WEBENCH® Tools
      2. 13.1.2 Third-Party Products Disclaimer
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Support Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.5 Electrical Characteristics

Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over TJ = -40°C to 125°C. Unless otherwise stated, VBIAS = 12V, RT = 9.09kΩ
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
SUPPLY CURRENT
ISHUTDOWN(BIAS)BIAS shutdown currentVBIAS = 12 V, VUVLO = 0 V2.65uA
IOPERATING(BIAS)BIAS operating currentVBIAS = 12 V, VUVLO = 2.0 V, VFB = VREF, RT = 220 kΩ490550uA
VCC REGULATOR
VVCC-REGVCC regulationVBIAS = 8 V, No load6.56.857V
VCC regulationVBIAS = 8 V, IVCC = 35 mA6.5V
VVCC-UVLO(RISING)VCC UVLO thresholdVCC rising2.752.852.95V
VCC UVLO hysteresisVCC falling0.063V
IVCC-CLVCC sourcing current limitVBIAS = 10 V, VVCC = 0 V35110mA
ENABLE
VEN(RISING)Enable thresholdEN rising0.40.520.7V
VEN(FALLING)Enable thresholdEN falling0.330.490.63V
VEN(HYS)Enable hysteresisEN falling0.03V
UVLO/SYNC
VUVLO(RISING)UVLO / SYNC thresholdUVLO rising1.4251.51.575V
VUVLO(FALLING)UVLO / SYNC thresholdUVLO falling1.3701.451.520V
VUVLO(HYS)UVLO / SYNC threshold hysteresisUVLO falling0.05V
IUVLOUVLO hysteresis currentVUVLO = 1.6 V456uA
SPREAD SPECTRUM
VDITHOFF(RISING)Clock dithering thresholdDITHOFF rising, VBIAS = 4 V1.11.72.1V
VDITHOFF(FALLING)Clock dithering thresholdDITHOFF falling, VBIAS = 4 V0.61.21.8V
VDITHOFF(HYS)Clock dithering threshold hysteresisDITHOFF falling, VBIAS = 4 V0.5V
SS
ISSSoft-start current91011uA
SS pull-down switch RDSON55Ω
PULSE WIDTH MODULATION
fsw1Switching frequencyRT = 220 kΩ, VBIAS = 4 V85100115kHz
fsw2Switching frequencyRT = 9.09 kΩ, VBIAS = 4 V198022002420kHz
tON(MIN)Minimum on-timeRT = 9.09 kΩ50ns
DMAX1Maximum duty cycle limitRT = 9.09 kΩ, VBIAS = 4 V808590%
DMAX2Maximum duty cycle limitRT = 220 kΩ, VBIAS = 4 V909396%
CURRENT SENSE
ISLOPEPeak slope compensation currentRT = 220 kΩ22.53037.5uA
VCLTHCurrent Limit threshold (CS-GND)93100107mV
HICCUP MODE PROTECTION (LM51561)
Hiccup enable cycles64Cycles
Hiccup timer reset cycles8Cycles
ERROR AMPLIFIER
VREFFB referenceLM5156, LM515610.9911.01V
GmTransconductance2mA/V
COMP sourcing currentVCOMP = 1.2V180uA
COMP clamp voltageCOMP rising (VUVLO = 2.0 V)2.52.8V
COMP clamp voltageCOMP falling11.1V
OVP
VOVTHOver-voltage thresholdFB rising (referece to VREF)107110113%
Over-voltage thresholdFB falling (referece to VREF)105%
PGOOD
PGOOD pull-down switch RDSON1 mA sinking90Ω
VUVTHUnder-voltage thresholdFB falling (referece to VREF)879093%
Under-voltage thresholdFB rising (referece to VREF)95%
MOSFET DRIVER
High-state voltage drop100 mA sinking0.25V
Low-state voltage drop100 mA sourcing0.15V
THERMAL SHUTDOWN
TTSDThermal shutdown thresholdTemperature rising175°C
Thermal shutdown hysteresis15°C