SNVSAE4C July 2015 – October 2018 LM5160-Q1
PRODUCTION DATA.
The following table summarizes the dual threshold levels of the undervoltage lockout (EN/UVLO) circuit explained in Enable / Undervoltage Lockout (EN/UVLO).
EN/UVLO PIN VOLTAGE | VCC REGULATOR | MODE | DESCRIPTION |
---|---|---|---|
< 0.35 V | Off | Shutdown | VCC regulator disabled. High-side and low-side FETs disabled. |
0.35 V to 1.24 V | On | Standby | VCC regulator enabled. High-side and low-side FETs disabled. |
> 1.24 V | VCC < VCC(UV) | Standby | VCC regulator enabled. High-side and low-side FETs disabled. |
VCC > VCC(UV) | Operating | VCC regulator enabled. Switching enabled. |
If input UVLO is not required, EN/UVLO can be driven by a logic signal as an enable input or connected directly to VIN. If EN/UVLO is directly connected to VIN, the regulator begins switching when VCC(UV) = 3.98 V (typical) is satisfied.