SNVSBN8A December   2019  – April 2023 LM5163H-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Control Architecture
      2. 7.3.2  Internal VCC Regulator and Bootstrap Capacitor
      3. 7.3.3  Regulation Comparator
      4. 7.3.4  Internal Soft Start
      5. 7.3.5  On-Time Generator
      6. 7.3.6  Current Limit
      7. 7.3.7  N-Channel Buck Switch and Driver
      8. 7.3.8  Synchronous Rectifier
      9. 7.3.9  Enable/Undervoltage Lockout (EN/UVLO)
      10. 7.3.10 Power Good (PGOOD)
      11. 7.3.11 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Active Mode
      3. 7.4.3 Sleep Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 High Temperature Specifications
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Switching Frequency (RRON)
        3. 8.2.2.3 Buck Inductor (LO)
        4. 8.2.2.4 Output Capacitor (COUT)
        5. 8.2.2.5 Input Capacitor (CIN)
        6. 8.2.2.6 Type 3 Ripple Network
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Compact PCB Layout for EMI Reduction
        2. 8.4.1.2 Feedback Resistors
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
      2. 9.1.2 Development Support
        1. 9.1.2.1 Custom Design with WEBENCH® Tools
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.2.6 Type 3 Ripple Network

A Type 3 ripple generation network uses an RC filter consisting of RA and CA across SW and VOUT to generate a triangular ramp that is in phase with the inductor current. This triangular ramp is then AC-coupled into the feedback node using capacitor CB as shown in Figure 8-1. Type 3 ripple injection is suited for applications where low output voltage ripple is crucial.

Use Equation 24 and Equation 25 to calculate RA and CA to provide the required ripple amplitude at the FB pin.

Equation 24. C A ≥ 10 F S W × R F B 1 | | R F B 2

For the feedback resistor values given in Figure 8-1, Equation 24 dictates a minimum CA of 742 pF. In this design, a 3300 pF capacitance is chosen. This is done to keep RA within practical limits between 100 kΩ and 1 MΩ when using Equation 25.

Equation 25. R A × C A ≥ V I N ( n o m ) - V O U T × t O N ( n o m ) 20 m V

Based on CA set at 3.3 nF, RA is calculated to be 226 kΩ to provide a 20-mV ripple voltage at FB. The general recommendation for a Type 3 network is to calculate RA and CA to get 20 mV of ripple at typical operating conditions, while ensuring a 12-mV minimum ripple voltage on FB at minimum VIN.

While the amplitude of the generated ripple does not affect the output voltage ripple, it impacts the output regulation as it reflects as a DC error of approximately half the amplitude of the generated ripple. For example, a converter circuit with Type 3 network that generates a 40-mV ripple voltage at the feedback node has approximately 10-mV worse load regulation scaled up through the FB divider to VOUT than the same circuit that generates a 20-mV ripple at FB. Use Equation 26 to calculate the coupling capacitance CB.

Equation 26. C B ≥ t T R - s e t t l i n g 3 × R F B 1

where

  • tTR-settling is the desired load transient response settling time

CB calculates to 56 pF based on a 75-µs settling time. This value avoids excessive coupling capacitor discharge by the feedback resistors during sleep intervals when operating at light loads. To avoid capacitance fall-off with DC bias, use a C0G or NP0 dielectric capacitor for CB.