SNVSBN8A December 2019 – April 2023 LM5163H-Q1
PRODUCTION DATA
PIN | I/O(1) | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | GND | G | Ground connection for internal circuits |
2 | VIN | P/I | Regulator supply input pin to high-side power MOSFET and internal bias regulator. Connect directly to the input supply of the buck converter with short, low impedance paths. |
3 | EN/UVLO | I | Precision enable and undervoltage lockout (UVLO) programming pin. If the EN/UVLO voltage is below 1.1 V, the converter is in shutdown mode with all functions disabled. If the UVLO voltage is greater than 1.1 V and below 1.5 V, the converter is in standby mode with the internal VCC regulator operational and no switching. If the EN/UVLO voltage is above 1.5 V, the start-up sequence begins. |
4 | RON | I | On-time programming pin. A resistor between this pin and GND sets the buck switch on-time. |
5 | FB | I | Feedback input of voltage regulation comparator |
6 | PGOOD | O | Power good indicator. This pin is an open-drain output pin. Connect to a source voltage through an external pullup resistor between 10 kΩ to 100 kΩ. |
7 | BST | P/I | Bootstrap gate-drive supply. Required to connect a high-quality 2.2-nF 50-V X7R ceramic capacitor between BST and SW to bias the internal high-side gate driver. |
8 | SW | P | Switching node that is internally connected to the source of the high-side NMOS buck switch and the drain of the low-side NMOS synchronous rectifier. Connect to the switching node of the power inductor. |
— | EP | — | Exposed pad of the package. No internal electrical connection. Solder the EP to the GND pin and connect to a large copper plane to reduce thermal resistance. |