SNVSAQ6D November   2016  – August 2021 LM5170-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Bias Supply (VCC, VCCA)
      2. 8.3.2  Undervoltage Lockout (UVLO) and Master Enable or Disable
      3. 8.3.3  High Voltage Input (VIN, VINX)
      4. 8.3.4  Current Sense Amplifier
      5. 8.3.5  Control Commands
        1. 8.3.5.1 Channel Enable Commands (EN1, EN2)
        2. 8.3.5.2 Direction Command (DIR)
        3. 8.3.5.3 Channel Current Setting Commands (ISETA or ISETD)
      6. 8.3.6  Channel Current Monitor (IOUT1, IOUT2)
      7. 8.3.7  Cycle-by-Cycle Peak Current Limit (IPK)
      8. 8.3.8  Error Amplifier
      9. 8.3.9  Ramp Generator
      10. 8.3.10 Soft Start
        1. 8.3.10.1 Soft-Start Control by the SS Pin
        2. 8.3.10.2 Soft Start by MCU Through the ISET Pin
        3. 8.3.10.3 The SS Pin as the Restart Timer
      11. 8.3.11 Gate Drive Outputs, Dead Time Programming and Adaptive Dead Time (HO1, HO2, LO1, LO2, DT)
      12. 8.3.12 PWM Comparator
      13. 8.3.13 Oscillator (OSC)
      14. 8.3.14 Synchronization to an External Clock (SYNCIN, SYNCOUT)
      15. 8.3.15 Diode Emulation
      16. 8.3.16 Power MOSFET Failure Detection and Failure Protection (nFAULT, BRKG, BRKS)
        1. 8.3.16.1 Failure Detection Selection at the SYNCOUT Pin
        2. 8.3.16.2 Nominal Circuit Breaker Function
      17. 8.3.17 Overvoltage Protection (OVPA, OVPB)
        1. 8.3.17.1 HV-V- Port OVP (OVPA)
        2. 8.3.17.2 LV-Port OVP (OVPB)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Multiphase Configurations (SYNCOUT, OPT)
        1. 8.4.1.1 Multiphase in Star Configuration
        2. 8.4.1.2 Configuration of 2, 3, or 4 Phases in Master-Slave Daisy-Chain Configurations
        3. 8.4.1.3 Configuration of 6 or 8 Phases in Master-Slave Daisy-Chain Configurations
      2. 8.4.2 Multiphase Total Current Monitoring
    5. 8.5 Programming
      1. 8.5.1 Dynamic Dead Time Adjustment
      2. 8.5.2 Optional UVLO Programming
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Typical Key Waveforms
        1. 9.1.1.1 Typical Power-Up Sequence
        2. 9.1.1.2 One to Eight Phase Programming
      2. 9.1.2 Inner Current Loop Small Signal Models
        1. 9.1.2.1 Small Signal Model
        2. 9.1.2.2 Inner Current Loop Compensation
      3. 9.1.3 Compensating for the Non-Ideal Current Sense Resistor
      4. 9.1.4 Outer Voltage Loop Control
    2. 9.2 Typical Application
      1. 9.2.1 60-A, Dual-Phase, 48-V to 12-V Bidirectional Converter
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1  Determining the Duty Cycle
          2. 9.2.1.2.2  Oscillator Programming
          3. 9.2.1.2.3  Power Inductor, RMS and Peak Currents
          4. 9.2.1.2.4  Current Sense (RCS)
          5. 9.2.1.2.5  Current Setting Limits (ISETA or ISETD)
          6. 9.2.1.2.6  Peak Current Limit
          7. 9.2.1.2.7  Power MOSFETS
          8. 9.2.1.2.8  Bias Supply
          9. 9.2.1.2.9  Boot Strap
          10. 9.2.1.2.10 RAMP Generators
          11. 9.2.1.2.11 OVP
          12. 9.2.1.2.12 Dead Time
          13. 9.2.1.2.13 IOUT Monitors
          14. 9.2.1.2.14 UVLO Pin Usage
          15. 9.2.1.2.15 VIN Pin Configuration
          16. 9.2.1.2.16 Loop Compensation
          17. 9.2.1.2.17 Soft Start
          18. 9.2.1.2.18 ISET Pins
        3. 9.2.1.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
9.2.1.2.16 Loop Compensation

Assuming the total resistance along the current path including the external power cables, PCB current tracks, and battery internal impedances is 50 mΩ, according to Equation 36, the compensation network for the inner current loop is determined by:

Equation 77. GUID-68D101DA-09DB-4614-95F5-0B45EC3E93F3-low.gif

Selecting the closest standard values for the compensation network, namely,

RCOMP1 = RCOMP2 = 634 Ω

CCOMP1 = CCOMP2 = 150 nF

CHF1 = CHF2 = 1 nF

These initial component selections produce a total loop phase margin of 90°, which is larger than necessary. Fine tune the loop compensation by reselecting CCOMP1 = CCOMP2 = 15 nF, then the phase margin is 45° for an optimal dynamic performance.

Figure 9-12 shows the Bode Plots of the power plant, the compensation gain, and the resulting total open loop.

GUID-8591E3A3-E8CD-4BD7-9A35-5B0D97C32231-low.gifFigure 9-12 Bode Plots of the Example Converter