SNVSC75A April   2023  – July 2024 LM5171-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
      1. 6.1.1 Device Configurations (CFG) and I2C Address
      2. 6.1.2 Definition of IC Operation Modes
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Bias Supplies and Voltage Reference (VCC, VDD, and VREF)
      2. 6.3.2  Undervoltage Lockout (UVLO) and Controller Enable or Disable
      3. 6.3.3  High Voltage Inputs (HV1, HV2)
      4. 6.3.4  Current Sense Amplifier
      5. 6.3.5  Control Commands
        1. 6.3.5.1 Channel Enable Commands (EN1, EN2)
        2. 6.3.5.2 Direction Command (DIR1 and DIR2)
        3. 6.3.5.3 Channel Current Setting Commands (ISET1 and ISET2)
      6. 6.3.6  Channel Current Monitor (IMON1, IMON2)
        1. 6.3.6.1 Individual Channel Current Monitor
        2. 6.3.6.2 Multiphase Total Current Monitoring
      7. 6.3.7  Cycle-by-Cycle Peak Current Limit (IPK)
      8. 6.3.8  Inner Current Loop Error Amplifier
      9. 6.3.9  Outer Voltage Loop Error Amplifier
      10. 6.3.10 Soft Start, Diode Emulation, and Forced PWM Control (SS/DEM1 and SS/DEM2)
        1. 6.3.10.1 Soft-Start Control by the SS/DEM Pins
        2. 6.3.10.2 DEM Programming
        3. 6.3.10.3 FPWM Programming and Dynamic FPWM and DEM Change
        4. 6.3.10.4 SS Pin as the Restart Timer
          1. 6.3.10.4.1 Restart Timer in OVP
          2. 6.3.10.4.2 Restart Timer after a DIR Change
      11. 6.3.11 Gate Drive Outputs, Dead Time Programming and Adaptive Dead Time (HO1, HO2, LO1, LO2, DT/SD)
      12. 6.3.12 Emergency Latched Shutdown (DT/SD)
      13. 6.3.13 PWM Comparator
      14. 6.3.14 Oscillator (OSC)
      15. 6.3.15 Synchronization to an External Clock (SYNCI, SYNCO)
      16. 6.3.16 Overvoltage Protection (OVP)
      17. 6.3.17 Multiphase Configurations (SYNCO, OPT)
        1. 6.3.17.1 Multiphase in Star Configuration
        2. 6.3.17.2 Daisy-Chain Configurations for 2, 3, or 4 Phases parallel operations
        3. 6.3.17.3 Daisy-Chain configuration for 6 or 8 phases parallel operation
      18. 6.3.18 Thermal Shutdown
    4. 6.4 Programming
      1. 6.4.1 Dynamic Dead Time Adjustment
      2. 6.4.2 UVLO Programming
    5. 6.5 Registers
      1. 6.5.1 I2C Serial Interface
      2. 6.5.2 I2C Bus Operation
      3. 6.5.3 Clock Stretching
      4. 6.5.4 Data Transfer Formats
      5. 6.5.5 Single READ From a Defined Register Address
      6. 6.5.6 Sequential READ Starting From a Defined Register Address
      7. 6.5.7 Single WRITE to a Defined Register Address
      8. 6.5.8 Sequential WRITE Starting From A Defined Register Address
      9. 6.5.9 REGFIELD Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Small Signal Model
        1. 7.1.1.1 Current Loop Small Signal Model
        2. 7.1.1.2 Current Loop Compensation
        3. 7.1.1.3 Voltage Loop Small Signal Model
        4. 7.1.1.4 Voltage Loop Compensation
    2. 7.2 Typical Application
      1. 7.2.1 60A, Dual-Phase, 48V to 12V Bidirectional Converter
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1  Determining the Duty Cycle
          2. 7.2.1.2.2  Oscillator Programming
          3. 7.2.1.2.3  Power Inductor, RMS and Peak Currents
          4. 7.2.1.2.4  Current Sense (RCS)
          5. 7.2.1.2.5  Current Setting Limits (ISETx)
          6. 7.2.1.2.6  Peak Current Limit
          7. 7.2.1.2.7  Power MOSFETS
          8. 7.2.1.2.8  Bias Supply
          9. 7.2.1.2.9  Boot Strap
          10. 7.2.1.2.10 OVP
          11. 7.2.1.2.11 Dead Time
          12. 7.2.1.2.12 Channel Current Monitor (IMONx)
          13. 7.2.1.2.13 UVLO Pin Usage
          14. 7.2.1.2.14 HVx Pin Configuration
          15. 7.2.1.2.15 Loop Compensation
          16. 7.2.1.2.16 Soft Start
          17. 7.2.1.2.17 PWM to ISET Pins
          18. 7.2.1.2.18 Proper Termination of Unused Pins
        3. 7.2.1.3 Application Curves
          1. 7.2.1.3.1 Efficiency
          2. 7.2.1.3.2 Step Load Response
          3. 7.2.1.3.3 Dual-Channel Interleaving Operation
          4. 7.2.1.3.4 Typical Start Up and Shutdown
          5. 7.2.1.3.5 DEM and FPWM
          6. 7.2.1.3.6 Mode transition between DEM and FPWM
          7. 7.2.1.3.7 ISET Tracking and PreCharge
          8. 7.2.1.3.8 Protections
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Examples
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5.9 REGFIELD Registers

Table 6-4 lists the memory-mapped registers for the REGFIELD registers. All register offset addresses not listed in Table 6-4 should be considered as reserved locations and the register contents should not be modified.

Table 6-4 REGFIELD Registers
AddressAcronymRegister NameSection
3hCLEAR_FAULTSCLEAR_FAULTSSection 6.5.9.1
78hFAULT_STATUSFAULT_STATUSSection 6.5.9.2
D0hDEVICE_STATUS_1DEVICE_STATUS_1Section 6.5.9.3
D1hDEVICE_STATUS_2DEVICE_STATUS_2Section 6.5.9.4

Complex bit access types are encoded to fit into small table cells. Table 6-5 shows the codes that are used for access types in this section.

Table 6-5 REGFIELD Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

6.5.9.1 CLEAR_FAULTS Register (Address = 3h) [Reset = 00h]

CLEAR_FAULTS is shown in Table 6-6.

Return to the Table 6-4.

Clear all latched status flags in 0x78 register

Table 6-6 CLEAR_FAULTS Register Field Descriptions
BitFieldTypeResetDescription
7-0CLEAR_FAULTSR/W0hAccessing the address is enough to clear fault

6.5.9.2 FAULT_STATUS Register (Address = 78h) [Reset = 00h]

FAULT_STATUS is shown in Table 6-7.

Return to the Table 6-4.

Fault status

Table 6-7 FAULT_STATUS Register Field Descriptions
BitFieldTypeResetDescription
7IPK_FAULTR0hIPK float detection
0h = no fault
1h = fault
6VREF_FAULTR0hVREF to VDD short detection
0h = no fault
1h = fault
5BOOTUV1R0hBoot UV (HB-SW undervoltage) Channel 1
0h = no fault
1h = fault
4BOOTUV2R0hBoot UV (HB-SW undervoltage) Channel 2
0h = no fault
1h = fault
3ILIM1R0hCurrent limit Channel 1
0h = no fault
1h = fault
2ILIM2R0hCurrent limit Channel 2
0h = no fault
1h = fault
1OVPR0hOver voltage fault
0h = no fault
1h = fault
0TSDR0hThermal shutdown fault
0h = no fault
1h = fault

6.5.9.3 DEVICE_STATUS_1 Register (Address = D0h) [Reset = 00h]

DEVICE_STATUS_1 is shown in Table 6-8.

Return to the Table 6-4.

Informational bits about the part status

Table 6-8 DEVICE_STATUS_1 Register Field Descriptions
BitFieldTypeResetDescription
7EN1R0hChannel 1 enable status
0h = Channel 1 disabled
1h = Channel 1 enabled
6EN2R0hChannel 2 enable status
0h = Channel 2 disabled
1h = Channel 2 enabled
5DEM1R0hChannel 1 DEM status
0h = Channel 1 FPWM
1h = Channel 1 DEM
4DEM2R0hChannel 2 DEM status
0h = Channel 2 FPWM
1h = Channel 2 DEM
3DIR1R0hDIR 1 status
0h = DIR1 low
1h = DIR1 high
2DIR2R0hDIR 2 status
0h = DIR2 low
1h = DIR2 high
1DIR_INVALID1R0hInvalid DIR1 command
0h = Valid DIR1 command
1h = Invalid DIR1 command
0DIR_INVALID2R0hInvalid DIR2 command
0h = Valid DIR2 command
1h = Invalid DIR2 command

6.5.9.4 DEVICE_STATUS_2 Register (Address = D1h) [Reset = 00h]

DEVICE_STATUS_2 is shown in Table 6-9.

Return to the Table 6-4.

Informational bits about the part status

Table 6-9 DEVICE_STATUS_2 Register Field Descriptions
BitFieldTypeResetDescription
7OSC_FAULTR0hOSC short detection
0h = No OSC fault
1h = OSC fault
6UVLOR0hUVLO status
0h = Not in UVLO
1h = In UVLO (UVLO<2.5V)
5OPTR0hOPT pin status
0h = OPT low
1h = OPT high
4SS1_DONER0hSS channel 1 completion status
0h = SS1 not done
1h = SS1 done
3SS2_DONER0hSS channel 2 completion status
0h = SS2 not done
1h = SS2 done
2SDR0hSD/DT pin status
0h = Part not in SD
1h = Part in SD
1ADAPT_DTR0hAdaptive deadtime status
0h = No adaptive deadtime
1h = Adaptive deadtime
0VCC_UVR0hVCC UV status
0h = VCC not in UV
1h = VCC in UV