SNVSC75A April   2023  – July 2024 LM5171-Q1

ADVANCE INFORMATION  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
      1. 6.1.1 Device Configurations (CFG) and I2C Address
      2. 6.1.2 Definition of IC Operation Modes
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Bias Supplies and Voltage Reference (VCC, VDD, and VREF)
      2. 6.3.2  Undervoltage Lockout (UVLO) and Controller Enable or Disable
      3. 6.3.3  High Voltage Inputs (HV1, HV2)
      4. 6.3.4  Current Sense Amplifier
      5. 6.3.5  Control Commands
        1. 6.3.5.1 Channel Enable Commands (EN1, EN2)
        2. 6.3.5.2 Direction Command (DIR1 and DIR2)
        3. 6.3.5.3 Channel Current Setting Commands (ISET1 and ISET2)
      6. 6.3.6  Channel Current Monitor (IMON1, IMON2)
        1. 6.3.6.1 Individual Channel Current Monitor
        2. 6.3.6.2 Multiphase Total Current Monitoring
      7. 6.3.7  Cycle-by-Cycle Peak Current Limit (IPK)
      8. 6.3.8  Inner Current Loop Error Amplifier
      9. 6.3.9  Outer Voltage Loop Error Amplifier
      10. 6.3.10 Soft Start, Diode Emulation, and Forced PWM Control (SS/DEM1 and SS/DEM2)
        1. 6.3.10.1 Soft-Start Control by the SS/DEM Pins
        2. 6.3.10.2 DEM Programming
        3. 6.3.10.3 FPWM Programming and Dynamic FPWM and DEM Change
        4. 6.3.10.4 SS Pin as the Restart Timer
          1. 6.3.10.4.1 Restart Timer in OVP
          2. 6.3.10.4.2 Restart Timer after a DIR Change
      11. 6.3.11 Gate Drive Outputs, Dead Time Programming and Adaptive Dead Time (HO1, HO2, LO1, LO2, DT/SD)
      12. 6.3.12 Emergency Latched Shutdown (DT/SD)
      13. 6.3.13 PWM Comparator
      14. 6.3.14 Oscillator (OSC)
      15. 6.3.15 Synchronization to an External Clock (SYNCI, SYNCO)
      16. 6.3.16 Overvoltage Protection (OVP)
      17. 6.3.17 Multiphase Configurations (SYNCO, OPT)
        1. 6.3.17.1 Multiphase in Star Configuration
        2. 6.3.17.2 Daisy-Chain Configurations for 2, 3, or 4 Phases parallel operations
        3. 6.3.17.3 Daisy-Chain configuration for 6 or 8 phases parallel operation
      18. 6.3.18 Thermal Shutdown
    4. 6.4 Programming
      1. 6.4.1 Dynamic Dead Time Adjustment
      2. 6.4.2 UVLO Programming
    5. 6.5 Registers
      1. 6.5.1 I2C Serial Interface
      2. 6.5.2 I2C Bus Operation
      3. 6.5.3 Clock Stretching
      4. 6.5.4 Data Transfer Formats
      5. 6.5.5 Single READ From a Defined Register Address
      6. 6.5.6 Sequential READ Starting From a Defined Register Address
      7. 6.5.7 Single WRITE to a Defined Register Address
      8. 6.5.8 Sequential WRITE Starting From A Defined Register Address
      9. 6.5.9 REGFIELD Registers
  8. Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Small Signal Model
        1. 7.1.1.1 Current Loop Small Signal Model
        2. 7.1.1.2 Current Loop Compensation
        3. 7.1.1.3 Voltage Loop Small Signal Model
        4. 7.1.1.4 Voltage Loop Compensation
    2. 7.2 Typical Application
      1. 7.2.1 60A, Dual-Phase, 48V to 12V Bidirectional Converter
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1  Determining the Duty Cycle
          2. 7.2.1.2.2  Oscillator Programming
          3. 7.2.1.2.3  Power Inductor, RMS and Peak Currents
          4. 7.2.1.2.4  Current Sense (RCS)
          5. 7.2.1.2.5  Current Setting Limits (ISETx)
          6. 7.2.1.2.6  Peak Current Limit
          7. 7.2.1.2.7  Power MOSFETS
          8. 7.2.1.2.8  Bias Supply
          9. 7.2.1.2.9  Boot Strap
          10. 7.2.1.2.10 OVP
          11. 7.2.1.2.11 Dead Time
          12. 7.2.1.2.12 Channel Current Monitor (IMONx)
          13. 7.2.1.2.13 UVLO Pin Usage
          14. 7.2.1.2.14 HVx Pin Configuration
          15. 7.2.1.2.15 Loop Compensation
          16. 7.2.1.2.16 Soft Start
          17. 7.2.1.2.17 PWM to ISET Pins
          18. 7.2.1.2.18 Proper Termination of Unused Pins
        3. 7.2.1.3 Application Curves
          1. 7.2.1.3.1 Efficiency
          2. 7.2.1.3.2 Step Load Response
          3. 7.2.1.3.3 Dual-Channel Interleaving Operation
          4. 7.2.1.3.4 Typical Start Up and Shutdown
          5. 7.2.1.3.5 DEM and FPWM
          6. 7.2.1.3.6 Mode transition between DEM and FPWM
          7. 7.2.1.3.7 ISET Tracking and PreCharge
          8. 7.2.1.3.8 Protections
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Examples
  9. Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Voltage Loop Small Signal Model

When the current loop compensator is designed, the outer voltage loop can then be analyzed.

A system with np phases is shown in Figure 7-4.

LM5171-Q1 np phases system Figure 7-4 np phases system

The equavilent inductance and resistance are determined by

Equation 50. Lmnp=Lmnp
Equation 51. RSnp=RSnp
Equation 52. RCSnp=RCSnp
Equation 53. Rfnp=Rfnp

The buck mode duty cycle (d) to np phases inductor current transfer function is determined by the following:

Equation 54. Gidnp_BKs=np×i^Lmd^=VHVROUT_BK×1+sωZ_il_BK1+sω0np_BK×QnpBK+s2ω0np_BK2

where

Equation 55. R O U T _ B K = V L V n p × I L m a x
Equation 56. ω Z _ i l _ B K = 1 R O U T _ B K × C O U T _ B K
Equation 57. ω0np_BK=1Lmnp×COUT_BK
Equation 58. Q n p B K = 1 ω 0 n p _ B K × 1 L m n p R O U T _ B K + R E S R _ B K + R C S n p + R S n p × C O U T _ B K

For np phase, the equivalent open loop gain Tinp(s) can be obtained as

Equation 59. Tinps=Gcis×1VM×Gids×Rfnp

where

Figure 7-5 shows the outer voltage control loop and inner current loop.

LM5171-Q1 Voltage Loop and Current Loop
                    Block Diagram Figure 7-5 Voltage Loop and Current Loop Block Diagram

We can get ISET to output voltage (vO) close loop transfer function as:

Equation 60. Gvss=v^LVv^ISET=Gcis×1VM×Gvds1+Tinps

When selecting the crossover frequency of the buck voltage loop lower than the current loop crossover frequency, Gvs(s) can be simplified. For the denominator, Tinp(s) dominates, Equation 60 can be written as:

Equation 61. Gvss=v^LVv^ISET=Gcis×1VM×GvdsTinps=GvdsGids×Rfnp

The buck power plant duty cycle (d) to output voltage (vLV) transfer function is determined by :

Equation 62. G v d _ B K s = v ^ L V d ^ = V H V × 1 + s ω Z _ v l _ B K 1 + s ω 0 n p _ B K × Q n p B K + s 2 ω 0 n p _ B K 2

where

Equation 63. ω Z _ v l _ B K = 1 R E S R _ B K × C O U T _ B K

Substituting Equation 62 into Equation 61, a simplified ISET to output voltage (VLV) transfer function is determined by the following:

Equation 64. G v s _ B K s = v ^ L V v ^ I S E T = K d c _ B K × 1 + s ω Z _ v l _ B K 1 + s ω Z _ i l _ B K

where

Equation 65. Kdc_BK=ROUT_BKRfnp

Similarly, the boost power plant duty cycle (d) to output voltage (vHV) transfer function is determined by :

Equation 66. G v d _ B S T s = v ^ H V d ^ = V L V D ' 2 × 1 + s ω Z _ v l _ B S T 1 - s ω R H P Z 1 + s ω 0 n p _ B S T × Q n p B S T + s 2 ω 0 n p _ B S T 2

where

Equation 67. ω Z _ v l _ B S T = 1 R E S R _ B S T × C O U T _ B S T
Equation 68. ω R H P Z = R O U T _ B S T × D ' 2 L m n p

Substituting Equation 66 into Equation 61, a simplified ISET to output voltage (VHV) transfer function is determined by the following:

Equation 69. G v s _ B S T s = v ^ H V i ^ s e t = K d c _ B S T × 1 + s ω Z _ v l _ B S T 1 - s ω R H P Z 1 + s ω Z _ i l _ B S T

where

Equation 70. Kdc_BST=ROUT_BST×D'2×Rfnp