SNVSC75A April 2023 – July 2024 LM5171-Q1
ADVANCE INFORMATION
Figure 6-36 shows the format of a single write to a defined register address. First, the Controller issues a start condition followed by a seven-bit I 2 C address. Next, the Controller writes a zero to signify that it wishes to conduct a write operation. Upon receiving an acknowledge from the Peripheral, the Controller sends the eight-bit register address across the bus. Following a second acknowledge the device sets the I 2 C register address to the defined value and the Controller writes the eight-bit data value. Upon receiving a third acknowledge the device auto increments the I 2 C register address by one and the Controller issues a stop condition. This action concludes the register write.