Each channel of the LM5171-Q1 has a robust 5A (peak) half bridge driver to drive external N-channel power MOSFETs. As shown in Figure 6-14, the low-side drive is directly powered by VCC, and the high-side driver by the bootstrap capacitor C_BT. During the on-time of the low-side driver, the SW pin is pulled down to PGND and C_BT is charged by VCC through the boot diode D_BT. TI recommends selecting a 0.1µF or larger ceramic capacitor for C_BT, and an ultra-fast diode of 1A and 100V ratings for D_BT. TI also strongly recommends users to add a 2Ω to 5Ω resistor (R_BT) in series with D_BT to limit the surge charging current and improve the noise immunity of the high-side driver.

Figure 6-14 Bootstrap Circuit for High-Side Bias Supply (Only One Channel is Shown)

During start-up in buck mode, C_BT may not be charged initially; the LM5171-Q1 then holds off the high-side driver outputs (HO1 and HO2) and sends LO pulses of 100ns width in consecutive cycles to pre-charge C_BT. When the boot voltage is greater than the 6.5V boot UV threshold, the high-side drivers output PWM signals at the HO1 and HO2 pins for normal switching action. If the boot voltage becomes lower than the boot UV threshold voltage on the falling edge, the corresponding HO output pulls low until the boot voltage recovers to assume normal HO switching pulses. During normal buck mode operation, when the CBT voltage falls below the 6.5V boot UV threshold, the same precharge function starts by interrupting the normal switching until the boot voltage restores above the UV threshold. This helps prevent the power MOSFETs from running into linear mode by inadequate gate voltage. Note that the gate threshold voltage of the MOSFETs may raise to as high as 6V due to degradation over aging.

During start-up and normal operation in boost mode, C_BT is naturally charged by the normal turnon of the low side MOSFET, therefore there is no such 100-ns pre-charge pulse at the LO pins.

To prevent shoot-through between the high-side and low-side power MOSFETs on the same half bridge leg, two types of dead time schemes can be chosen with the DT pin: the programmable dead time or built-in adaptive dead time.

To program the dead time, place a resistor R_DT across the DT/SD and AGND pins as shown in Figure 6-15.

The dead time t_DT as depicted in Figure 6-16 is determined by Equation 14:

Note that this equation is valid for programming t_DT between 15ns and 200ns. When the power MOSFET is connected to the gate drive, its gate input capacitance C_ISS becomes a load of the gate drive output, and the HO and LO slew rate are reduced, leading to a reduced effective t_DT between the high- and low-side MOSFETs. The user must evaluate the effective t_DT to make sure it is adequate to prevent shoot-through between the high- and low-side MOSFETs.

When the DT programmability is not used, simply connect the DT/SD pin to VDD as shown in Figure 6-17, to activate the built-in adaptive dead time. The adaptive dead time is implemented by real time monitoring of the output of a driver (either HO or LO) by the other driver (LO or HO) of the same half bridge switch leg, as shown in Figure 6-17 and Figure 6-18. Only when the output voltage of a driver falls below 1.5V does the other driver starts turnon. The effectiveness of adaptive dead time is greatly reduced if a series gate resistor is used, or if the PCB traces of the gate drive have excessive impedance due to poor layout design.

Figure 6-15 Dead Time Programming With DT Pin (Only One Channel is Shown)

Figure 6-16 Gate Drive Dead Time (Only One Channel is Shown)

Figure 6-17 Dead Time without external Programming (Only One Channel is Shown)

Figure 6-18 Adaptive Dead Time (Only One Channel is Shown)