SNVSC75A April   2023  – July 2024 LM5171-Q1

ADVANCE INFORMATION  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
      1. 6.1.1 Device Configurations (CFG) and I2C Address
      2. 6.1.2 Definition of IC Operation Modes
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Bias Supplies and Voltage Reference (VCC, VDD, and VREF)
      2. 6.3.2  Undervoltage Lockout (UVLO) and Controller Enable or Disable
      3. 6.3.3  High Voltage Inputs (HV1, HV2)
      4. 6.3.4  Current Sense Amplifier
      5. 6.3.5  Control Commands
        1. 6.3.5.1 Channel Enable Commands (EN1, EN2)
        2. 6.3.5.2 Direction Command (DIR1 and DIR2)
        3. 6.3.5.3 Channel Current Setting Commands (ISET1 and ISET2)
      6. 6.3.6  Channel Current Monitor (IMON1, IMON2)
        1. 6.3.6.1 Individual Channel Current Monitor
        2. 6.3.6.2 Multiphase Total Current Monitoring
      7. 6.3.7  Cycle-by-Cycle Peak Current Limit (IPK)
      8. 6.3.8  Inner Current Loop Error Amplifier
      9. 6.3.9  Outer Voltage Loop Error Amplifier
      10. 6.3.10 Soft Start, Diode Emulation, and Forced PWM Control (SS/DEM1 and SS/DEM2)
        1. 6.3.10.1 Soft-Start Control by the SS/DEM Pins
        2. 6.3.10.2 DEM Programming
        3. 6.3.10.3 FPWM Programming and Dynamic FPWM and DEM Change
        4. 6.3.10.4 SS Pin as the Restart Timer
          1. 6.3.10.4.1 Restart Timer in OVP
          2. 6.3.10.4.2 Restart Timer after a DIR Change
      11. 6.3.11 Gate Drive Outputs, Dead Time Programming and Adaptive Dead Time (HO1, HO2, LO1, LO2, DT/SD)
      12. 6.3.12 Emergency Latched Shutdown (DT/SD)
      13. 6.3.13 PWM Comparator
      14. 6.3.14 Oscillator (OSC)
      15. 6.3.15 Synchronization to an External Clock (SYNCI, SYNCO)
      16. 6.3.16 Overvoltage Protection (OVP)
      17. 6.3.17 Multiphase Configurations (SYNCO, OPT)
        1. 6.3.17.1 Multiphase in Star Configuration
        2. 6.3.17.2 Daisy-Chain Configurations for 2, 3, or 4 Phases parallel operations
        3. 6.3.17.3 Daisy-Chain configuration for 6 or 8 phases parallel operation
      18. 6.3.18 Thermal Shutdown
    4. 6.4 Programming
      1. 6.4.1 Dynamic Dead Time Adjustment
      2. 6.4.2 UVLO Programming
    5. 6.5 Registers
      1. 6.5.1 I2C Serial Interface
      2. 6.5.2 I2C Bus Operation
      3. 6.5.3 Clock Stretching
      4. 6.5.4 Data Transfer Formats
      5. 6.5.5 Single READ From a Defined Register Address
      6. 6.5.6 Sequential READ Starting From a Defined Register Address
      7. 6.5.7 Single WRITE to a Defined Register Address
      8. 6.5.8 Sequential WRITE Starting From A Defined Register Address
      9. 6.5.9 REGFIELD Registers
  8. Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Small Signal Model
        1. 7.1.1.1 Current Loop Small Signal Model
        2. 7.1.1.2 Current Loop Compensation
        3. 7.1.1.3 Voltage Loop Small Signal Model
        4. 7.1.1.4 Voltage Loop Compensation
    2. 7.2 Typical Application
      1. 7.2.1 60A, Dual-Phase, 48V to 12V Bidirectional Converter
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1  Determining the Duty Cycle
          2. 7.2.1.2.2  Oscillator Programming
          3. 7.2.1.2.3  Power Inductor, RMS and Peak Currents
          4. 7.2.1.2.4  Current Sense (RCS)
          5. 7.2.1.2.5  Current Setting Limits (ISETx)
          6. 7.2.1.2.6  Peak Current Limit
          7. 7.2.1.2.7  Power MOSFETS
          8. 7.2.1.2.8  Bias Supply
          9. 7.2.1.2.9  Boot Strap
          10. 7.2.1.2.10 OVP
          11. 7.2.1.2.11 Dead Time
          12. 7.2.1.2.12 Channel Current Monitor (IMONx)
          13. 7.2.1.2.13 UVLO Pin Usage
          14. 7.2.1.2.14 HVx Pin Configuration
          15. 7.2.1.2.15 Loop Compensation
          16. 7.2.1.2.16 Soft Start
          17. 7.2.1.2.17 PWM to ISET Pins
          18. 7.2.1.2.18 Proper Termination of Unused Pins
        3. 7.2.1.3 Application Curves
          1. 7.2.1.3.1 Efficiency
          2. 7.2.1.3.2 Step Load Response
          3. 7.2.1.3.3 Dual-Channel Interleaving Operation
          4. 7.2.1.3.4 Typical Start Up and Shutdown
          5. 7.2.1.3.5 DEM and FPWM
          6. 7.2.1.3.6 Mode transition between DEM and FPWM
          7. 7.2.1.3.7 ISET Tracking and PreCharge
          8. 7.2.1.3.8 Protections
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Examples
  9. Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Current Loop Small Signal Model

Figure 7-1 shows the current loop block diagram of each phase in buck mode. VHV is the input while VLV is the output.

LM5171-Q1 Buck Loop Block
          Diagram Figure 7-1 Buck Loop Block Diagram

The inner current loop should be designed first. The average current-mode control loop of buck mode can be modeled asFigure 7-2

LM5171-Q1 Current Loop
          Block Diagram Figure 7-2 Current Loop Block Diagram

The buck mode duty cycle (d) to channel inductor current (iLm) transfer function is determined by the following:

Equation 23. Gid_BKs=i^Lmd^=VHVROUT_BK×1+sωZ_il_BK1+sω0_BK×QBK+s2ω0_BK2

where

Equation 24. ROUT_BK=VLVnp×ILmax
Equation 25. ω Z _ i l _ B K = 1 R O U T _ B K × C O U T _ B K
Equation 26. ω 0 _ B K = 1 L m × C O U T _ B K
Equation 27. Q B K = 1 ω 0 _ B K × 1 L m R O U T _ B K + R E S R _ B K + R C S + R S × C O U T _ B K
  • Lm is the power inductor,
  • RCS is the current sense resistor,
  • RS is the equivalent total resistance along the current path excluding RCS,
  • COUT_BK is the total output capacitance in buck mode.
  • RESR_BK is the total output capacitor equivalent series resistance (ESR).

Figure 7-3 shows the current loop block diagram in boost mode. VLV is the input while VHV is the output.

LM5171-Q1 Boost Loop Block Diagram Figure 7-3 Boost Loop Block Diagram

The average current-mode control loop of boost mode is the same as buck as shown in Figure 7-2. But the transfer function of the boost power stage Gid(s) and Gvd(s) is different from that of buck power stage.

The boost mode duty cycle (d) to channel inductor current (iLm) transfer function is determined by the following:

Equation 28. G i d _ B S T s = i ^ L m d ^ = 2 × V L V D ' 3 × R O U T _ B S T × 1 + s ω Z _ i l _ B S T 1 + s ω 0 _ B S T × Q B S T + s 2 ω 0 _ B S T 2

where

Equation 29. D ' = V L V V H V
Equation 30. R O U T _ B S T = V H V 2 V L V × I L m a x
Equation 31. ω Z _ i l _ B S T = 2 R O U T _ B S T × C O U T _ B S T
Equation 32. ω 0 _ B S T = D ' L m × C O U T _ B S T
Equation 33. Q B S T = D ' ω 0 _ B S T × 1 L m D ' × R O U T _ B S T + R C S + R S × C O U T _ B S T D ' + R E S R _ B S T × C O U T _ B S T
  • COUT_BST is the total output capacitance for each phase in boost mode.
  • RESR_BST is the total output capacitor equivalent series resistance (ESR) for each phase in boost mode.

When we select the current loop cross over frequency at 1/6 of switching frequency, Gid_BK(s) can be simplified. For the numerator, s×ROUT_BK×COUT_BK dominates. And for the denominator, s20_BK2 dominates.Equation 23 can be simplified as:

Equation 34. G i d _ B K s = V H V R O U T _ B K × 1 + s ω Z _ i l _ B K s 2 ω 0 _ B K 2 = V H V s × L m

Similarly, Equation 28 can be simplified as:

Equation 35. G i d _ B S T s = 2 × V L V D ' 3 × R O U T _ B S T × s ω Z _ i l _ B S T s 2 ω 0 _ B S T 2 = V H V s × L m

It can be observed that the same duty cycle (d) to channel inductor current (iLm) transfer function is shared by both buck and boost mode:

Equation 36. G i d s = V H V s × L m

So compensator for buck current loop and boost current loop can also be shared.