SNVSCM3
June 2024
LM5171
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics
5.6
Timing Requirements
5.7
Typical Characteristics
6
Detailed Description
6.1
Overview
6.1.1
Device Configurations (CFG) and I2C Address
6.1.2
Definition of IC Operation Modes
6.2
Functional Block Diagram
6.3
Feature Description
6.3.1
Bias Supplies and Voltage Reference (VCC, VDD, and VREF)
6.3.2
Undervoltage Lockout (UVLO) and Controller Enable or Disable
6.3.3
High Voltage Inputs (HV1, HV2)
6.3.4
Current Sense Amplifier
6.3.5
Control Commands
6.3.5.1
Channel Enable Commands (EN1, EN2)
6.3.5.2
Direction Command (DIR1 and DIR2)
6.3.5.3
Channel Current Setting Commands (ISET1 and ISET2)
6.3.6
Channel Current Monitor (IMON1, IMON2)
6.3.6.1
Individual Channel Current Monitor
6.3.6.2
Multiphase Total Current Monitoring
6.3.7
Cycle-by-Cycle Peak Current Limit (IPK)
6.3.8
Inner Current Loop Error Amplifier
6.3.9
Outer Voltage Loop Error Amplifier
6.3.10
Soft Start, Diode Emulation, and Forced PWM Control (SS/DEM1 and SS/DEM2)
6.3.10.1
Soft-Start Control by the SS/DEM Pins
6.3.10.2
DEM Programming
6.3.10.3
FPWM Programming and Dynamic FPWM and DEM Change
6.3.10.4
SS Pin as the Restart Timer
6.3.10.4.1
Restart Timer in OVP
6.3.10.4.2
Restart Timer after a DIR Change
6.3.11
Gate Drive Outputs, Dead Time Programming and Adaptive Dead Time (HO1, HO2, LO1, LO2, DT/SD)
6.3.12
Emergency Latched Shutdown (DT/SD)
6.3.13
PWM Comparator
6.3.14
Oscillator (OSC)
6.3.15
Synchronization to an External Clock (SYNCI, SYNCO)
6.3.16
Overvoltage Protection (OVP)
6.3.17
Multiphase Configurations (SYNCO, OPT)
6.3.17.1
Multiphase in Star Configuration
6.3.17.2
Daisy-Chain Configurations for 2, 3, or 4 Phases parallel operations
6.3.17.3
Daisy-Chain configuration for 6 or 8 phases parallel operation
6.3.18
Thermal Shutdown
6.4
Programming
6.4.1
Dynamic Dead Time Adjustment
6.4.2
UVLO Programming
6.5
Registers
6.5.1
I2C Serial Interface
6.5.2
I2C Bus Operation
6.5.3
Clock Stretching
6.5.4
Data Transfer Formats
6.5.5
Single READ From a Defined Register Address
6.5.6
Sequential READ Starting From a Defined Register Address
6.5.7
Single WRITE to a Defined Register Address
6.5.8
Sequential WRITE Starting From A Defined Register Address
6.5.9
REGFIELD Registers
7
Application and Implementation
7.1
Application Information
7.1.1
Small Signal Model
7.1.1.1
Current Loop Small Signal Model
7.1.1.2
Current Loop Compensation
7.1.1.3
Voltage Loop Small Signal Model
7.1.1.4
Voltage Loop Compensation
7.2
Typical Application
7.2.1
60A, Dual-Phase, 48V to 12V Bidirectional Converter
7.2.1.1
Design Requirements
7.2.1.2
Detailed Design Procedure
7.2.1.2.1
Determining the Duty Cycle
7.2.1.2.2
Oscillator Programming
7.2.1.2.3
Power Inductor, RMS and Peak Currents
7.2.1.2.4
Current Sense (RCS)
7.2.1.2.5
Current Setting Limits (ISETx)
7.2.1.2.6
Peak Current Limit
7.2.1.2.7
Power MOSFETS
7.2.1.2.8
Bias Supply
7.2.1.2.9
Boot Strap
7.2.1.2.10
OVP
7.2.1.2.11
Dead Time
7.2.1.2.12
Channel Current Monitor (IMONx)
7.2.1.2.13
UVLO Pin Usage
7.2.1.2.14
HVx Pin Configuration
7.2.1.2.15
Loop Compensation
7.2.1.2.16
Soft Start
7.2.1.2.17
PWM to ISET Pins
7.2.1.2.18
Proper Termination of Unused Pins
7.2.1.3
Application Curves
7.2.1.3.1
Efficiency
7.2.1.3.2
Step Load Response
7.2.1.3.3
Dual-Channel Interleaving Operation
7.2.1.3.4
Typical Start Up and Shutdown
7.2.1.3.5
DEM and FPWM
7.2.1.3.6
Mode transition between DEM and FPWM
7.2.1.3.7
ISET Tracking and PreCharge
7.2.1.3.8
Protections
7.3
Power Supply Recommendations
7.4
Layout
7.4.1
Layout Guidelines
7.4.2
Layout Examples
8
Device and Documentation Support
8.1
Device Support
8.1.1
Development Support
8.2
Receiving Notification of Documentation Updates
8.3
Support Resources
8.4
Trademarks
8.5
Electrostatic Discharge Caution
8.6
Glossary
9
Revision History
10
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
PHP|48
MPQF051B
Thermal pad, mechanical data (Package|Pins)
PHP|48
PPTD259B
Orderable Information
snvscm3_oa
8.1.1
Development Support
For development support, see the following:
LM5170
LM25118
LM5118
LM5158
LM5160
LM5161