SNVSCM3 June 2024 LM5171
PRODUCTION DATA
PIN | I/O(1) | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | VREF | P | Output of the built-in 3.5V +/- 1% reference voltage. |
2 | FBLV | I | The inverting input pin for the buck error voltage amplifier. |
3 | ERRLV | O | Output pin of the buck error voltage amplifier. |
4 | IMON2 | O | CH-2 current monitor pin. |
5 | CSA2 | I | CH-2 differential current sense inputs. |
6 | CSB2 | I | |
7 | ISET2 | I | CH-2 analog current programming pin. |
8 | COMP2 | O | Output of the CH-2 transconductance (gm) error amplifier and the inverting input of the CH-2 PWM comparator. |
9 | SS/DEM2 | I | The soft-start programming pin for CH-2 controller. It also sets CH-2 in either DEM or FPWM. |
10 | EN2 | I | CH-2 enable pin. |
11 | DIR2 | I | CH-2 direction command input. |
12 | VDD | P | Output of 5V internal LDO. |
13 | HV2 | I | The input pin connecting to the HV-Port line voltage for CH-2 controller. |
14 | HB2 | I | CH-2 high-side gate driver bootstrap supply input. |
15 | HO2 | O | CH-2 high-side gate driver output. |
16 | SW2 | P | CH-2 switch node. |
17 | LO2 | O | CH-2 low-side gate driver output. |
18 | PGND | G | Power ground connection pin. |
19 | VCC | P | VCC bias supply pin. |
20 | LO1 | O | CH-1 low-side gate driver output. |
21 | SW1 | P | CH-1 switch node. |
22 | HO1 | O | CH-1 high-side gate driver output. |
23 | HB1 | I | CH-1 high-side gate driver bootstrap supply input. |
24 | HV1 | I | The input pin connecting to the HV-Port line voltage for CH-1 controller. |
25 | LDODRV | O | Control pin for the external VCC LDO MOSFET. |
26 | DIR1 | I | CH-1 direction command input. |
27 | EN1 | I | CH-1 enable pin. |
28 | SS/DEM1 | I | The soft-start programming pin for CH-1 controller. It also sets CH-1 in either DEM or FPWM. |
29 | COMP1 | O | Output of the CH-1 trans-conductance (gm) error amplifier and the inverting input of the CH-1 PWM comparator. |
30 | ISET1 | I | CH-1 analog current programming pin. |
31 | CSB1 | I | CH-1 differential current sense inputs. |
32 | CSA1 | I | |
33 | IMON1 | O | CH-1 current monitor pin. |
34 | ERRHV | O | Output pin of the boost error voltage amplifier. |
35 | FBHV | I | The inverting input pin for the boost error voltage amplifier. |
36 | OVP | I | Input of the built-in over-voltage comparator. |
37 | SDA | I/O | Data of I2C interface. |
38 | SCL | I | Clock of I2C interface. |
39 | SYNCO | O | Clock synchronization output pin. |
40 | SYNCI | I | Clock synchronization input pin. |
41 | OPT | I | Multiphase configuration pin. |
42 | OSC | I | The internal oscillator frequency programming pin. |
43 | AGND | G | Analog ground reference. |
44 | CFG | I | The I2C address setting and current monitor mode selection pin. |
45 | UVLO | I | The UVLO pin, which also serves as the Controller-Peripheral enable pin. |
46 | DT/SD | I | Dead-time programming and emergent latched shutdown pin. |
47 | IPK | I | Peak current limit programming pin. |
48 | VSET | I | Voltage error amplifier reference input pin. |
— | EP | — | Exposed pad of the package. |