SNVSCM3 June   2024 LM5171

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
      1. 6.1.1 Device Configurations (CFG) and I2C Address
      2. 6.1.2 Definition of IC Operation Modes
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Bias Supplies and Voltage Reference (VCC, VDD, and VREF)
      2. 6.3.2  Undervoltage Lockout (UVLO) and Controller Enable or Disable
      3. 6.3.3  High Voltage Inputs (HV1, HV2)
      4. 6.3.4  Current Sense Amplifier
      5. 6.3.5  Control Commands
        1. 6.3.5.1 Channel Enable Commands (EN1, EN2)
        2. 6.3.5.2 Direction Command (DIR1 and DIR2)
        3. 6.3.5.3 Channel Current Setting Commands (ISET1 and ISET2)
      6. 6.3.6  Channel Current Monitor (IMON1, IMON2)
        1. 6.3.6.1 Individual Channel Current Monitor
        2. 6.3.6.2 Multiphase Total Current Monitoring
      7. 6.3.7  Cycle-by-Cycle Peak Current Limit (IPK)
      8. 6.3.8  Inner Current Loop Error Amplifier
      9. 6.3.9  Outer Voltage Loop Error Amplifier
      10. 6.3.10 Soft Start, Diode Emulation, and Forced PWM Control (SS/DEM1 and SS/DEM2)
        1. 6.3.10.1 Soft-Start Control by the SS/DEM Pins
        2. 6.3.10.2 DEM Programming
        3. 6.3.10.3 FPWM Programming and Dynamic FPWM and DEM Change
        4. 6.3.10.4 SS Pin as the Restart Timer
          1. 6.3.10.4.1 Restart Timer in OVP
          2. 6.3.10.4.2 Restart Timer after a DIR Change
      11. 6.3.11 Gate Drive Outputs, Dead Time Programming and Adaptive Dead Time (HO1, HO2, LO1, LO2, DT/SD)
      12. 6.3.12 Emergency Latched Shutdown (DT/SD)
      13. 6.3.13 PWM Comparator
      14. 6.3.14 Oscillator (OSC)
      15. 6.3.15 Synchronization to an External Clock (SYNCI, SYNCO)
      16. 6.3.16 Overvoltage Protection (OVP)
      17. 6.3.17 Multiphase Configurations (SYNCO, OPT)
        1. 6.3.17.1 Multiphase in Star Configuration
        2. 6.3.17.2 Daisy-Chain Configurations for 2, 3, or 4 Phases parallel operations
        3. 6.3.17.3 Daisy-Chain configuration for 6 or 8 phases parallel operation
      18. 6.3.18 Thermal Shutdown
    4. 6.4 Programming
      1. 6.4.1 Dynamic Dead Time Adjustment
      2. 6.4.2 UVLO Programming
    5. 6.5 Registers
      1. 6.5.1 I2C Serial Interface
      2. 6.5.2 I2C Bus Operation
      3. 6.5.3 Clock Stretching
      4. 6.5.4 Data Transfer Formats
      5. 6.5.5 Single READ From a Defined Register Address
      6. 6.5.6 Sequential READ Starting From a Defined Register Address
      7. 6.5.7 Single WRITE to a Defined Register Address
      8. 6.5.8 Sequential WRITE Starting From A Defined Register Address
      9. 6.5.9 REGFIELD Registers
  8. Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Small Signal Model
        1. 7.1.1.1 Current Loop Small Signal Model
        2. 7.1.1.2 Current Loop Compensation
        3. 7.1.1.3 Voltage Loop Small Signal Model
        4. 7.1.1.4 Voltage Loop Compensation
    2. 7.2 Typical Application
      1. 7.2.1 60A, Dual-Phase, 48V to 12V Bidirectional Converter
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1  Determining the Duty Cycle
          2. 7.2.1.2.2  Oscillator Programming
          3. 7.2.1.2.3  Power Inductor, RMS and Peak Currents
          4. 7.2.1.2.4  Current Sense (RCS)
          5. 7.2.1.2.5  Current Setting Limits (ISETx)
          6. 7.2.1.2.6  Peak Current Limit
          7. 7.2.1.2.7  Power MOSFETS
          8. 7.2.1.2.8  Bias Supply
          9. 7.2.1.2.9  Boot Strap
          10. 7.2.1.2.10 OVP
          11. 7.2.1.2.11 Dead Time
          12. 7.2.1.2.12 Channel Current Monitor (IMONx)
          13. 7.2.1.2.13 UVLO Pin Usage
          14. 7.2.1.2.14 HVx Pin Configuration
          15. 7.2.1.2.15 Loop Compensation
          16. 7.2.1.2.16 Soft Start
          17. 7.2.1.2.17 PWM to ISET Pins
          18. 7.2.1.2.18 Proper Termination of Unused Pins
        3. 7.2.1.3 Application Curves
          1. 7.2.1.3.1 Efficiency
          2. 7.2.1.3.2 Step Load Response
          3. 7.2.1.3.3 Dual-Channel Interleaving Operation
          4. 7.2.1.3.4 Typical Start Up and Shutdown
          5. 7.2.1.3.5 DEM and FPWM
          6. 7.2.1.3.6 Mode transition between DEM and FPWM
          7. 7.2.1.3.7 ISET Tracking and PreCharge
          8. 7.2.1.3.8 Protections
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Examples
  9. Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Gate Drive Outputs, Dead Time Programming and Adaptive Dead Time (HO1, HO2, LO1, LO2, DT/SD)

Each channel of the LM5171 has a robust 5A (peak) half bridge driver to drive external N-channel power MOSFETs. As shown in Figure 6-14, the low-side drive is directly powered by VCC, and the high-side driver by the bootstrap capacitor CBT. During the on-time of the low-side driver, the SW pin is pulled down to PGND and CBT is charged by VCC through the boot diode DBT. TI recommends selecting a 0.1µF or larger ceramic capacitor for CBT, and an ultra-fast diode of 1A and 100V ratings for DBT. TI also strongly recommends users to add a 2Ω to 5Ω resistor (RBT) in series with DBT to limit the surge charging current and improve the noise immunity of the high-side driver.

LM5171 Bootstrap
                    Circuit for High-Side Bias Supply (Only One Channel is Shown) Figure 6-14 Bootstrap Circuit for High-Side Bias Supply (Only One Channel is Shown)

During start-up in buck mode, CBT may not be charged initially; the LM5171 then holds off the high-side driver outputs (HO1 and HO2) and sends LO pulses of 100ns width in consecutive cycles to pre-charge CBT. When the boot voltage is greater than the 6.5V boot UV threshold, the high-side drivers output PWM signals at the HO1 and HO2 pins for normal switching action. If the boot voltage becomes lower than the boot UV threshold voltage on the falling edge, the corresponding HO output pulls low until the boot voltage recovers to assume normal HO switching pulses. During normal buck mode operation, when the CBT voltage falls below the 6.5V boot UV threshold, the same precharge function starts by interrupting the normal switching until the boot voltage restores above the UV threshold. This helps prevent the power MOSFETs from running into linear mode by inadequate gate voltage. Note that the gate threshold voltage of the MOSFETs may raise to as high as 6V due to degradation over aging.

During start-up and normal operation in boost mode, CBT is naturally charged by the normal turnon of the low side MOSFET, therefore there is no such 100-ns pre-charge pulse at the LO pins.

To prevent shoot-through between the high-side and low-side power MOSFETs on the same half bridge leg, two types of dead time schemes can be chosen with the DT pin: the programmable dead time or built-in adaptive dead time.

To program the dead time, place a resistor RDT across the DT/SD and AGND pins as shown in Figure 6-15.

The dead time tDT as depicted in Figure 6-16 is determined by Equation 14:

Equation 14. t D T   = R D T × 2.625 n s k

Note that this equation is valid for programming tDT between 15ns and 200ns. When the power MOSFET is connected to the gate drive, its gate input capacitance CISS becomes a load of the gate drive output, and the HO and LO slew rate are reduced, leading to a reduced effective tDT between the high- and low-side MOSFETs. The user must evaluate the effective tDT to make sure it is adequate to prevent shoot-through between the high- and low-side MOSFETs.

When the DT programmability is not used, simply connect the DT/SD pin to VDD as shown in Figure 6-17, to activate the built-in adaptive dead time. The adaptive dead time is implemented by real time monitoring of the output of a driver (either HO or LO) by the other driver (LO or HO) of the same half bridge switch leg, as shown in Figure 6-17 and Figure 6-18. Only when the output voltage of a driver falls below 1.5V does the other driver starts turnon. The effectiveness of adaptive dead time is greatly reduced if a series gate resistor is used, or if the PCB traces of the gate drive have excessive impedance due to poor layout design.

LM5171 Dead Time
                    Programming With DT Pin (Only One Channel is Shown) Figure 6-15 Dead Time Programming With DT Pin (Only One Channel is Shown)
LM5171 Gate
                    Drive Dead Time (Only One Channel is Shown) Figure 6-16 Gate Drive Dead Time (Only One Channel is Shown)
LM5171 Dead Time
                    without external Programming (Only One Channel is Shown) Figure 6-17 Dead Time without external Programming (Only One Channel is Shown)
LM5171 Adaptive
                    Dead Time (Only One Channel is Shown) Figure 6-18 Adaptive Dead Time (Only One Channel is Shown)