SNVSCM3 June 2024 LM5171
PRODUCTION DATA
The LM5171 integrates a LDO driver to drive an external N-channel MOSFET to generate a 9V bias supply at the VCC pin. The VCC pin can also accept an external supply of 9.5V to 12V and the device turns off the LDO driver to save the power dissipation in the external LDO MOSFET. Figure 6-1 shows typical connections of the bias supply.
When external supply is used, it is recommended to add a block diode to prevent from discharging the VCC during transient in the external supply. If an external supply voltage is greater than 12V, a 10V LDO or switching regulator must be used to produce 10V for VCC. The VCC voltage is directly fed to the low-side MOSFET drivers. A 1μF to 2.2μF ceramic capacitance must be placed between the VCC and PGND pins to bypass the driver switching currents. For the LDO MOSFET, it is recommended to have the Ciss around 300pF or below.
The internal VCC undervoltage (UV) detection circuit monitors the VCC voltage. When the VCC voltage falls below 8V on the falling edge, the LM5171 is held in the shutdown state. For normal operation, the VCC voltage must be greater than 8.5V on the rising edge.
Once the VCC voltage is above the VCC_UV, the VDD and VREF regulator turns on to establish 5.0V and 3.5V, respectively. The VDD regulator can supply up to 10 mA to the external circuit. The VREF is a 1% accurate reference voltage for the external circuit to use, and it has a loading capability of 2mA. A ceramic capacitance between 0.5μF to 2.0uF must be placed between VDD and AGND pins, and 0.1 μF between VREF and AGND pins, respectively.