SNVSCM3 June   2024 LM5171

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
      1. 6.1.1 Device Configurations (CFG) and I2C Address
      2. 6.1.2 Definition of IC Operation Modes
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Bias Supplies and Voltage Reference (VCC, VDD, and VREF)
      2. 6.3.2  Undervoltage Lockout (UVLO) and Controller Enable or Disable
      3. 6.3.3  High Voltage Inputs (HV1, HV2)
      4. 6.3.4  Current Sense Amplifier
      5. 6.3.5  Control Commands
        1. 6.3.5.1 Channel Enable Commands (EN1, EN2)
        2. 6.3.5.2 Direction Command (DIR1 and DIR2)
        3. 6.3.5.3 Channel Current Setting Commands (ISET1 and ISET2)
      6. 6.3.6  Channel Current Monitor (IMON1, IMON2)
        1. 6.3.6.1 Individual Channel Current Monitor
        2. 6.3.6.2 Multiphase Total Current Monitoring
      7. 6.3.7  Cycle-by-Cycle Peak Current Limit (IPK)
      8. 6.3.8  Inner Current Loop Error Amplifier
      9. 6.3.9  Outer Voltage Loop Error Amplifier
      10. 6.3.10 Soft Start, Diode Emulation, and Forced PWM Control (SS/DEM1 and SS/DEM2)
        1. 6.3.10.1 Soft-Start Control by the SS/DEM Pins
        2. 6.3.10.2 DEM Programming
        3. 6.3.10.3 FPWM Programming and Dynamic FPWM and DEM Change
        4. 6.3.10.4 SS Pin as the Restart Timer
          1. 6.3.10.4.1 Restart Timer in OVP
          2. 6.3.10.4.2 Restart Timer after a DIR Change
      11. 6.3.11 Gate Drive Outputs, Dead Time Programming and Adaptive Dead Time (HO1, HO2, LO1, LO2, DT/SD)
      12. 6.3.12 Emergency Latched Shutdown (DT/SD)
      13. 6.3.13 PWM Comparator
      14. 6.3.14 Oscillator (OSC)
      15. 6.3.15 Synchronization to an External Clock (SYNCI, SYNCO)
      16. 6.3.16 Overvoltage Protection (OVP)
      17. 6.3.17 Multiphase Configurations (SYNCO, OPT)
        1. 6.3.17.1 Multiphase in Star Configuration
        2. 6.3.17.2 Daisy-Chain Configurations for 2, 3, or 4 Phases parallel operations
        3. 6.3.17.3 Daisy-Chain configuration for 6 or 8 phases parallel operation
      18. 6.3.18 Thermal Shutdown
    4. 6.4 Programming
      1. 6.4.1 Dynamic Dead Time Adjustment
      2. 6.4.2 UVLO Programming
    5. 6.5 Registers
      1. 6.5.1 I2C Serial Interface
      2. 6.5.2 I2C Bus Operation
      3. 6.5.3 Clock Stretching
      4. 6.5.4 Data Transfer Formats
      5. 6.5.5 Single READ From a Defined Register Address
      6. 6.5.6 Sequential READ Starting From a Defined Register Address
      7. 6.5.7 Single WRITE to a Defined Register Address
      8. 6.5.8 Sequential WRITE Starting From A Defined Register Address
      9. 6.5.9 REGFIELD Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Small Signal Model
        1. 7.1.1.1 Current Loop Small Signal Model
        2. 7.1.1.2 Current Loop Compensation
        3. 7.1.1.3 Voltage Loop Small Signal Model
        4. 7.1.1.4 Voltage Loop Compensation
    2. 7.2 Typical Application
      1. 7.2.1 60A, Dual-Phase, 48V to 12V Bidirectional Converter
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1  Determining the Duty Cycle
          2. 7.2.1.2.2  Oscillator Programming
          3. 7.2.1.2.3  Power Inductor, RMS and Peak Currents
          4. 7.2.1.2.4  Current Sense (RCS)
          5. 7.2.1.2.5  Current Setting Limits (ISETx)
          6. 7.2.1.2.6  Peak Current Limit
          7. 7.2.1.2.7  Power MOSFETS
          8. 7.2.1.2.8  Bias Supply
          9. 7.2.1.2.9  Boot Strap
          10. 7.2.1.2.10 OVP
          11. 7.2.1.2.11 Dead Time
          12. 7.2.1.2.12 Channel Current Monitor (IMONx)
          13. 7.2.1.2.13 UVLO Pin Usage
          14. 7.2.1.2.14 HVx Pin Configuration
          15. 7.2.1.2.15 Loop Compensation
          16. 7.2.1.2.16 Soft Start
          17. 7.2.1.2.17 PWM to ISET Pins
          18. 7.2.1.2.18 Proper Termination of Unused Pins
        3. 7.2.1.3 Application Curves
          1. 7.2.1.3.1 Efficiency
          2. 7.2.1.3.2 Step Load Response
          3. 7.2.1.3.3 Dual-Channel Interleaving Operation
          4. 7.2.1.3.4 Typical Start Up and Shutdown
          5. 7.2.1.3.5 DEM and FPWM
          6. 7.2.1.3.6 Mode transition between DEM and FPWM
          7. 7.2.1.3.7 ISET Tracking and PreCharge
          8. 7.2.1.3.8 Protections
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Examples
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4.1 Layout Guidelines

Careful PCB layout is critical to achieve low EMI and stable power supply operation as well as optimal efficiency. Make the high frequency current loops as small as possible, and follow these guidelines of good layout practices:

  1. For high power board design, use at least a 4-layer PCB of 2oz or thicker copper planes. Make the first inner layer a ground plane that is adjacent to the top layer on which the power components are installed, and use the second inner layer for the critical control signals including the current sense, gate drive, commands, and so forth. The ground plane between the signal and top layers helps shield switching noises on the top layer away from affecting the control signals.
  2. Optimize the component placements and orientations before routing any traces. Place the power components such that the power flow from port to port is direct, straight and short. Avoid making the power flow path zigzag on the board.
  3. Identify the high frequency AC current loops. In the bidirectional converter, the AC current loop of each channel is along the path of the HV-port rail capacitors, high-side MOSFET, low-side MOSFET, and back to the return of the HV-port rail capacitor. Place these components such that the current flow path is short, direct and the special area enclosed by the loop is minimized.
  4. Place the power circuit symmetrically between CH-1 and CH-2. Split the HV-port rail capacitors and LV-port rail capacitors evenly between CH-1 and CH-2.
  5. If more than one LM5171 is used on the same PCB for multi phases, place the circuits of each LM5171 in the similar pattern.
  6. Use adequate copper for the power circuit, so as to minimize the conduction losses on high-current PCB tracks. Adequate copper can also help dissipate the heat generated by the power components, especially the power inductors, power MOSFETs, and current sense resistors. However, pay attention to the polygon of the switch node, which connects the high-side MOSFET source, low-side MOSFET drain, power inductor, and the controller SW pin. The switch node polygon sees high dv/dt during switching operation. To minimize the EMI emission by the switch node polygon, make its size sufficient but not excessive to conduct the switched current.
  7. Use appropriate number of via holes to conduct current to, and heat through, the inner layers.
  8. Always separate the power ground from the analog ground, and make a single point connection of the power ground, analog ground, and the EP pad, at the location of the PGND pin.
  9. Minimize current-sensing errors by routing each pair of CSA and CSB traces using a kelvin-sensing directly across the current sense resistors. The pair of traces must be routed closely side by side for good noise immunity.
  10. Route sensitive analog signals of the CS, FBLV, FBHV, IPK, VSET, IMON, COMP and OVP pins away from the high-speed switching nodes (HB, HO, LO, and SW).
  11. Route the paired gate drive traces, namely the pairs of HO1 and SW1, HO2 and SW2, LO1 and return, and LO2 and return, closely side by side. Route CH-1 gate drive traces in symmetry with that of CH-2.
  12. Place the device setting, programming and controlling components as close as possible to the corresponding pins, including the following component: ROSC, RCFG, RDT, , CCOMP1, RCOMP2, CCOMP1, CCOPM2, CHF1, CHF2, RHVC, RLVC, CHVC, CLVC, CHVHF and CLVHF.
  13. Place the bypass capacitors as close as possible to the corresponding pins, including CHV, CVCC, CVDD, CVREF, CVSET, CHB1, CHB2, COVP, CIPK, CISET, CCS1, CCS2 as well as the 100-pF current sense common-mode bypassing capacitors.
  14. Flood each layer with copper to take up the empty areas for optimal thermal performance.
  15. Apply heat sink to components as necessary according to the system requirements.