SNVSCM3 June   2024 LM5171

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
      1. 6.1.1 Device Configurations (CFG) and I2C Address
      2. 6.1.2 Definition of IC Operation Modes
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Bias Supplies and Voltage Reference (VCC, VDD, and VREF)
      2. 6.3.2  Undervoltage Lockout (UVLO) and Controller Enable or Disable
      3. 6.3.3  High Voltage Inputs (HV1, HV2)
      4. 6.3.4  Current Sense Amplifier
      5. 6.3.5  Control Commands
        1. 6.3.5.1 Channel Enable Commands (EN1, EN2)
        2. 6.3.5.2 Direction Command (DIR1 and DIR2)
        3. 6.3.5.3 Channel Current Setting Commands (ISET1 and ISET2)
      6. 6.3.6  Channel Current Monitor (IMON1, IMON2)
        1. 6.3.6.1 Individual Channel Current Monitor
        2. 6.3.6.2 Multiphase Total Current Monitoring
      7. 6.3.7  Cycle-by-Cycle Peak Current Limit (IPK)
      8. 6.3.8  Inner Current Loop Error Amplifier
      9. 6.3.9  Outer Voltage Loop Error Amplifier
      10. 6.3.10 Soft Start, Diode Emulation, and Forced PWM Control (SS/DEM1 and SS/DEM2)
        1. 6.3.10.1 Soft-Start Control by the SS/DEM Pins
        2. 6.3.10.2 DEM Programming
        3. 6.3.10.3 FPWM Programming and Dynamic FPWM and DEM Change
        4. 6.3.10.4 SS Pin as the Restart Timer
          1. 6.3.10.4.1 Restart Timer in OVP
          2. 6.3.10.4.2 Restart Timer after a DIR Change
      11. 6.3.11 Gate Drive Outputs, Dead Time Programming and Adaptive Dead Time (HO1, HO2, LO1, LO2, DT/SD)
      12. 6.3.12 Emergency Latched Shutdown (DT/SD)
      13. 6.3.13 PWM Comparator
      14. 6.3.14 Oscillator (OSC)
      15. 6.3.15 Synchronization to an External Clock (SYNCI, SYNCO)
      16. 6.3.16 Overvoltage Protection (OVP)
      17. 6.3.17 Multiphase Configurations (SYNCO, OPT)
        1. 6.3.17.1 Multiphase in Star Configuration
        2. 6.3.17.2 Daisy-Chain Configurations for 2, 3, or 4 Phases parallel operations
        3. 6.3.17.3 Daisy-Chain configuration for 6 or 8 phases parallel operation
      18. 6.3.18 Thermal Shutdown
    4. 6.4 Programming
      1. 6.4.1 Dynamic Dead Time Adjustment
      2. 6.4.2 UVLO Programming
    5. 6.5 Registers
      1. 6.5.1 I2C Serial Interface
      2. 6.5.2 I2C Bus Operation
      3. 6.5.3 Clock Stretching
      4. 6.5.4 Data Transfer Formats
      5. 6.5.5 Single READ From a Defined Register Address
      6. 6.5.6 Sequential READ Starting From a Defined Register Address
      7. 6.5.7 Single WRITE to a Defined Register Address
      8. 6.5.8 Sequential WRITE Starting From A Defined Register Address
      9. 6.5.9 REGFIELD Registers
  8. Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Small Signal Model
        1. 7.1.1.1 Current Loop Small Signal Model
        2. 7.1.1.2 Current Loop Compensation
        3. 7.1.1.3 Voltage Loop Small Signal Model
        4. 7.1.1.4 Voltage Loop Compensation
    2. 7.2 Typical Application
      1. 7.2.1 60A, Dual-Phase, 48V to 12V Bidirectional Converter
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1  Determining the Duty Cycle
          2. 7.2.1.2.2  Oscillator Programming
          3. 7.2.1.2.3  Power Inductor, RMS and Peak Currents
          4. 7.2.1.2.4  Current Sense (RCS)
          5. 7.2.1.2.5  Current Setting Limits (ISETx)
          6. 7.2.1.2.6  Peak Current Limit
          7. 7.2.1.2.7  Power MOSFETS
          8. 7.2.1.2.8  Bias Supply
          9. 7.2.1.2.9  Boot Strap
          10. 7.2.1.2.10 OVP
          11. 7.2.1.2.11 Dead Time
          12. 7.2.1.2.12 Channel Current Monitor (IMONx)
          13. 7.2.1.2.13 UVLO Pin Usage
          14. 7.2.1.2.14 HVx Pin Configuration
          15. 7.2.1.2.15 Loop Compensation
          16. 7.2.1.2.16 Soft Start
          17. 7.2.1.2.17 PWM to ISET Pins
          18. 7.2.1.2.18 Proper Termination of Unused Pins
        3. 7.2.1.3 Application Curves
          1. 7.2.1.3.1 Efficiency
          2. 7.2.1.3.2 Step Load Response
          3. 7.2.1.3.3 Dual-Channel Interleaving Operation
          4. 7.2.1.3.4 Typical Start Up and Shutdown
          5. 7.2.1.3.5 DEM and FPWM
          6. 7.2.1.3.6 Mode transition between DEM and FPWM
          7. 7.2.1.3.7 ISET Tracking and PreCharge
          8. 7.2.1.3.8 Protections
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Examples
  9. Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Current Loop Compensation

Equation 36 indicates that the power plant is basically a first-order system. A Type-II compensator as shown in Figure 7-1 is adequate to stabilize the loop for both buck and boost mode operations.

Assuming the output impedance of the gm amplifier is RGM, the current loop compensation gain is determined by :

Equation 37. G c i s = G m × R G M Z c o m p s

where

  • ACS is the current sense amplifier gain, that is 40;
  • Gm is the trans-conductance of the gm error amplifier, which is 100μA/V;
  • ZCOMP(s) is the equivalent impedance of the compensation network seen at the COMP pin (see Figure 7-1)
Equation 38. Z C O M P s = 1 C H F + C C O M P × 1 + s × R C O M P × C C O M P s × 1 + s × R C O M P × C H F × C C O M P C H F + C C O M P

Considering CHF << CCOMP, Equation 38 can be simplified to :

Equation 39. Z C O M P s = 1 C C O M P × 1 + s × R C O M P × C C O M P s × 1 + s × R C O M P × C H F

Because RGM is > 5MegΩ, and the frequency range for loop compensation is usually above a few kHz, the effects of RGM on the loop gain in the interested frequency range becomes negligible. Therefore, substituting Equation 39 into Equation 37, and neglecting RGM, one can get the following:

Equation 40. G c i s = G m C C O M P × 1 + s × R C O M P × C C O M P s × 1 + s × R C O M P × C H F

From Figure 7-2, the open-loop gain of the inner current loop can be found as:

Equation 41. Tis=Gcis×1VM×Gids×Rf

where

Equation 42. V M = V H V × K F F
Equation 43. Rf=RCS×ACS

  • KFF is the ramp generator coefficient. For LM5171, KFF=0.03125.

Substituting Equation 40 and Equation 36 into Equation 41, Ti(s) can be written as:

Equation 44. Tis=1s×KFF×Lm×Rf×GmCCOMP×1+s×RCOMP×CCOMPs×1+s×RCOMP×CHF

The poles and zeros of the total loop transfer function are determined by:

Equation 45. f p 1 = 0
Equation 46. f p 2 = 1 2 π × R C O M P × C H F
Equation 47. f z = 1 2 π × R C O M P × C C O M P

To tailor the total inner current loop gain to crossover at fCI, select the components of the compensation network according to the following guidelines, then fine tune the network for optimal loop performance.

  1. The zero fz is placed at around 1/5 of target crossover frequency fCI,
  2. The pole fp2 is placed at approximately 1/2 of switching frequency fSW,
  3. The total open-loop gain is set to unity at fCI, namely,

Equation 48. T i 2 i × π × f C I = 1

Therefore, the compensation components can be derived from the above equations, as shown in Equation 49.

Equation 49. R C O M P = K F F A C S × R C S × G m × 2 i × π × f C I × L m C C O M P = 1 2 i × π × f C I 5 × R C O M P C H F = 1 2 i × π × f S W 2 × R C O M P