SNVSCM3 June   2024 LM5171

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
      1. 6.1.1 Device Configurations (CFG) and I2C Address
      2. 6.1.2 Definition of IC Operation Modes
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Bias Supplies and Voltage Reference (VCC, VDD, and VREF)
      2. 6.3.2  Undervoltage Lockout (UVLO) and Controller Enable or Disable
      3. 6.3.3  High Voltage Inputs (HV1, HV2)
      4. 6.3.4  Current Sense Amplifier
      5. 6.3.5  Control Commands
        1. 6.3.5.1 Channel Enable Commands (EN1, EN2)
        2. 6.3.5.2 Direction Command (DIR1 and DIR2)
        3. 6.3.5.3 Channel Current Setting Commands (ISET1 and ISET2)
      6. 6.3.6  Channel Current Monitor (IMON1, IMON2)
        1. 6.3.6.1 Individual Channel Current Monitor
        2. 6.3.6.2 Multiphase Total Current Monitoring
      7. 6.3.7  Cycle-by-Cycle Peak Current Limit (IPK)
      8. 6.3.8  Inner Current Loop Error Amplifier
      9. 6.3.9  Outer Voltage Loop Error Amplifier
      10. 6.3.10 Soft Start, Diode Emulation, and Forced PWM Control (SS/DEM1 and SS/DEM2)
        1. 6.3.10.1 Soft-Start Control by the SS/DEM Pins
        2. 6.3.10.2 DEM Programming
        3. 6.3.10.3 FPWM Programming and Dynamic FPWM and DEM Change
        4. 6.3.10.4 SS Pin as the Restart Timer
          1. 6.3.10.4.1 Restart Timer in OVP
          2. 6.3.10.4.2 Restart Timer after a DIR Change
      11. 6.3.11 Gate Drive Outputs, Dead Time Programming and Adaptive Dead Time (HO1, HO2, LO1, LO2, DT/SD)
      12. 6.3.12 Emergency Latched Shutdown (DT/SD)
      13. 6.3.13 PWM Comparator
      14. 6.3.14 Oscillator (OSC)
      15. 6.3.15 Synchronization to an External Clock (SYNCI, SYNCO)
      16. 6.3.16 Overvoltage Protection (OVP)
      17. 6.3.17 Multiphase Configurations (SYNCO, OPT)
        1. 6.3.17.1 Multiphase in Star Configuration
        2. 6.3.17.2 Daisy-Chain Configurations for 2, 3, or 4 Phases parallel operations
        3. 6.3.17.3 Daisy-Chain configuration for 6 or 8 phases parallel operation
      18. 6.3.18 Thermal Shutdown
    4. 6.4 Programming
      1. 6.4.1 Dynamic Dead Time Adjustment
      2. 6.4.2 UVLO Programming
    5. 6.5 Registers
      1. 6.5.1 I2C Serial Interface
      2. 6.5.2 I2C Bus Operation
      3. 6.5.3 Clock Stretching
      4. 6.5.4 Data Transfer Formats
      5. 6.5.5 Single READ From a Defined Register Address
      6. 6.5.6 Sequential READ Starting From a Defined Register Address
      7. 6.5.7 Single WRITE to a Defined Register Address
      8. 6.5.8 Sequential WRITE Starting From A Defined Register Address
      9. 6.5.9 REGFIELD Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Small Signal Model
        1. 7.1.1.1 Current Loop Small Signal Model
        2. 7.1.1.2 Current Loop Compensation
        3. 7.1.1.3 Voltage Loop Small Signal Model
        4. 7.1.1.4 Voltage Loop Compensation
    2. 7.2 Typical Application
      1. 7.2.1 60A, Dual-Phase, 48V to 12V Bidirectional Converter
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1  Determining the Duty Cycle
          2. 7.2.1.2.2  Oscillator Programming
          3. 7.2.1.2.3  Power Inductor, RMS and Peak Currents
          4. 7.2.1.2.4  Current Sense (RCS)
          5. 7.2.1.2.5  Current Setting Limits (ISETx)
          6. 7.2.1.2.6  Peak Current Limit
          7. 7.2.1.2.7  Power MOSFETS
          8. 7.2.1.2.8  Bias Supply
          9. 7.2.1.2.9  Boot Strap
          10. 7.2.1.2.10 OVP
          11. 7.2.1.2.11 Dead Time
          12. 7.2.1.2.12 Channel Current Monitor (IMONx)
          13. 7.2.1.2.13 UVLO Pin Usage
          14. 7.2.1.2.14 HVx Pin Configuration
          15. 7.2.1.2.15 Loop Compensation
          16. 7.2.1.2.16 Soft Start
          17. 7.2.1.2.17 PWM to ISET Pins
          18. 7.2.1.2.18 Proper Termination of Unused Pins
        3. 7.2.1.3 Application Curves
          1. 7.2.1.3.1 Efficiency
          2. 7.2.1.3.2 Step Load Response
          3. 7.2.1.3.3 Dual-Channel Interleaving Operation
          4. 7.2.1.3.4 Typical Start Up and Shutdown
          5. 7.2.1.3.5 DEM and FPWM
          6. 7.2.1.3.6 Mode transition between DEM and FPWM
          7. 7.2.1.3.7 ISET Tracking and PreCharge
          8. 7.2.1.3.8 Protections
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Examples
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
7.2.1.2.12 Channel Current Monitor (IMONx)

For best current monitor accuracy, choose IMONx resistor that the maximum operating voltage on the IMONx pin is less than 3V.

Considering two phase current monitoring with maximum 50A for each channel, and make sure IMONx voltage no more than 3V, RIMONx can be find as:

Equation 105. RIMONx = 10kΩ

Choose CIMONx considering delay and voltage ripple. Here we select:

Equation 106. CIMONx = 10nF

Then the delay of the monitor is determined by the following time constant:

Equation 107. τIMONx=RIMONx×CIMONx=10kΩ×10ns=100μs

At full load, the DC component of the monitor voltage is:

Equation 108. VIMONx=2×Imax×RCS500Ω+50μA×RIMONx=2×30A×1mΩ500Ω+50μA×10kΩ=2.2V

Considering the inductor ripple current, according to Equation 6, the IOUT peak to peak ripple current is:

Equation 109. Δ I M O N x = I p k - p k × R C S 500 Ω = 23.8 A × 1 m Ω 500 Ω = 47.6 μ A

The RC filter corner frequency is thus given by:

Equation 110. fIMONx=12π×RIMONx×CIMONx=16.28×10kΩ×10nF=1.59kHz

The resulting peak-to-peak monitor ripple voltage is approximately determined by:

Equation 111. ΔVIMONx=ΔIMONx×RIMONx12i×π×FSW×CIMONx=47.6μA×10kΩ12i×π×100kHz×10nF=7.5mV

The peak-to-peak monitor ripple voltage is approximately 0.34% of the full load DC monitor voltage. Increasing CIMONx attenuates the ripple voltage at the cost of higher monitor delay.