SNVSCL2 December   2024 LM51770

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Gate Driver Rise Time and Fall Time
    2. 7.2 Gate Driver Dead (Transition) Time
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Power-On Reset (POR System)
      2. 8.3.2  Buck-Boost Control Scheme
        1. 8.3.2.1 Boost Mode
        2. 8.3.2.2 Buck Mode
        3. 8.3.2.3 Buck-Boost Mode
      3. 8.3.3  Power Save Mode
      4. 8.3.4  Supply Voltage Selection – VMAX Switch
      5. 8.3.5  Enable and Undervoltage Lockout
      6. 8.3.6  Oscillator Frequency Selection
      7. 8.3.7  Frequency Synchronization
      8. 8.3.8  Voltage Regulation Loop
      9. 8.3.9  Output Voltage Tracking
      10. 8.3.10 Slope Compensation
      11. 8.3.11 Configurable Soft Start
      12. 8.3.12 Peak Current Sensor
      13. 8.3.13 Current Monitoring and Current Limit Control Loop
      14. 8.3.14 Short Circuit - Hiccup Protection
      15. 8.3.15 nFLT Pin and Protections
      16. 8.3.16 Device Configuration Pin
      17. 8.3.17 Dual Random Spread Spectrum – DRSS
      18. 8.3.18 Gate Driver
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Detailed Design Procedure
        1. 9.2.1.1  Custom Design with WEBENCH Tools
        2. 9.2.1.2  Frequency
        3. 9.2.1.3  Feedback Divider
        4. 9.2.1.4  Inductor and Current Sense Resistor Selection
        5. 9.2.1.5  Slope Compensation
        6. 9.2.1.6  Output Capacitor
        7. 9.2.1.7  Input Capacitor
        8. 9.2.1.8  UVLO Divider
        9. 9.2.1.9  Soft-Start Capacitor
        10. 9.2.1.10 MOSFETs QH1 and QL1
        11. 9.2.1.11 MOSFETs QH2 and QL2
        12. 9.2.1.12 Frequency Compensation
        13. 9.2.1.13 External Component Selection
      2. 9.2.2 Application Curves
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Power Stage Layout
      2. 11.1.2 Gate Driver Layout
      3. 11.1.3 Controller Layout
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Development Support
        1. 12.1.2.1 Custom Design with WEBENCH Tools
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information
    1.     80

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.1.12 Frequency Compensation

This section presents the control loop compensation design procedure for the LM51770 buck-boost controller. The LM51770 operates mainly in buck or boost modes, separated by a transition region, and therefore, the control loop design is done for both buck and boost operating modes. Then, a final selection of compensation is made based on the mode that is more restrictive from a loop stability point of view. Typically, for a converter designed to go deep into both buck and boost operating regions, the boost compensation design is more restrictive due to the presence of a right half plane zero (RHPZ) in boost mode.

The boost power stage output pole location is given by:

Equation 39. f p 1 ( boost ) =   1 2 π 2 R OUT ×   C OUT =   1 . 22   kHz

where

  • ROUT = 2.0 Ω corresponds to the maximum load of 8.0 A.

The boost power stage ESR zero location is given by:

Equation 40. f z 1 =   1 2 π 1 R ESR ×   C OUT =   61.2   kHz

The boost power stage RHP zero location is given by:

Equation 41. f RHP =   1 2 π R OUT × ( 1 - D MAX ) 2 L 1 =   24 . 87   kHz

where

  • DMAX is the maximum duty cycle at the minimum VIN.

The buck power stage output pole location is given by:

Equation 42. f p 1 ( buck ) =   1 2 π 1 R OUT ×   C OUT = 612   Hz

The buck power stage ESR zero location is the same as the boost power stage ESR zero.

It is clear from Equation 43 that RHP zero is the main factor limiting the achievable bandwidth. For a robust design, the crossover frequency must be less than 1/3 of the RHP zero frequency. Given the position of the RHP zero, a reasonable target bandwidth in boost operation is around 5 kHz:

Equation 43. f bw =   5   kHz

For some power stages, the boost RHP zero may not be as restrictive, which happens when the boost maximum duty cycle (DMAX) is small, or when a really small inductor is used. In those cases, compare the limits posed by the RHP zero (fRHP / 3) with 1/20 of the switching frequency and use the smaller of the two values as the achievable bandwidth.

The compensation zero can be placed at 1.5 times the boost output pole frequency. Keep in mind that this locates the zero at three times the buck output pole frequency, which results in approximately 30 degrees of phase loss before crossover of the buck loop and 15 degrees of phase loss at intermediate frequencies for the boost loop:

Equation 44. f ZC =   1 . 8   kHz

The compensation gain resistor, Rc1, is calculated with:

Equation 45. R C 1 =   2 π × f bw gm EA × R FB 1 + R FB 2 R FB 2 × A CS × R CS × C OUT 1 - D MAX × 1 1 + f bw f RHP 2 = 1.9   kΩ

where

  • DMAX is the maximum duty cycle at the minimum VIN in boost mode.
  • ACS is the current sense amplifier gain.

The compensation capacitor, Cc1, is then calculated from:

Equation 46. C C 1 =   1 2 π × f ZC ×   R c 1 =   45.8 nF

The standard values of compensation components are selected to be Rc1 = 1.91 kΩ and Cc1 = 47 nF.

A high frequency pole (fpc2) is placed using a capacitor (Cc2) in parallel with Rc1 and Cc1. Set the frequency of this pole at seven to ten times of fbw to provide attenuation of switching ripple and noise on COMP while avoiding excessive phase loss at the crossover frequency. For a target fpc2 = 6 kHz, Cc2 is calculated using Equation 47:

Equation 47. C C 2 =   1 2 π × f pc 2 × R c 1 =   1 . 68   nF

Select a standard value of 1.8 nF for Cc2. These values provide a good starting point for the compensation design. Each design must be tuned in the lab to achieve the desired balance between stability margin across the operating range and transient response time.