The LM5190 is an 80V, ultra-low IQ, synchronous buck DC/DC controller with Constant-Current Constant-Voltage (CC-CV) regulation. The controller uses a peak current-mode control architecture for easy loop compensation, fast transient response, and excellent load and line regulation. The integrated CC-CV operation features a high accuracy for the regulation of both voltage (±1%) and current (±3%) . The CC-CV operation also provides seamless transition between constant-current and constant-voltage mode. The CC-CV operation effectively reduces the bill of materials (BOM) count and cost for applications that require average output current control. The output current limit is programmable and can be dynamically changed. The LM5190 has an output current monitor.
The LM5190 has a unique EMI reduction feature known as dual random spread spectrum (DRSS). Combining low-frequency triangular and high-frequency random modulations mitigates EMI disturbances across lower and higher frequency bands, respectively. This hybrid technique aligns with the multiple resolution bandwidth (RBW) settings specified in industry-standard EMC tests.
Additional features of the LM5190 include 150°C maximum junction temperature operation, user-selectable diode emulation for lower current consumption at light-load conditions, open-drain power-good flag for fault reporting and output monitoring, precision enable input, monotonic start-up into prebiased load, integrated dual-input VCC bias supply regulator, internal 2.75ms soft-start time, and thermal shutdown protection with automatic recovery.
The LM5190 controller comes in a 3.5mm × 4.5mm, thermally enhanced, 19-pin VQFN package.
PIN | TYPE(1) | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | ISET | I/O | Dynamic current setting pin for the constant-current operation |
2 | RT | I | Frequency programming pin. A resistor from RT to AGND sets the oscillator frequency between 100kHz and 2.2MHz and DRSS disabled. A resistor from RT to VCC sets the oscillator frequency between 100kHz and 2.2MHz and DRSS enabled. |
3 | COMP | O | Transconductance error amplifier output. Connect the compensation network from COMP to AGND. |
4 | FB | I | Connect FB to VCC during initial power on to set the output voltage to pre-programmed fixed 12V. Connect FB to AGND during initial power on to set the output voltage to pre-programmed fixed 5V. Alternatively, install a resistor divider from VOUT to AGND to set the output voltage setpoint between 0.8V and 79V. The FB regulation voltage is 0.8V. |
5 | AGND | G | Analog ground connection. Ground return for the internal voltage reference and analog circuits. |
6 | IMON/ILIM | O | Current monitor and current limit programming pin |
7 | VCC | P | VCC bias supply pin. Connect a ceramic capacitor between VCC and PGND. |
8 | PGND | G | Power ground connection pin for low-side MOSFET gate driver. |
9 | LO | P | Low-side power MOSFET gate driver output. |
10 | VIN | P | Supply voltage input source for the VCC regulator. |
11 | HO | P | High-side power MOSFET gate driver output. |
12 | SW | P | Switching node of the buck regulator and high-side gate driver return. Connect to the bootstrap capacitor, the source terminal of the high-side MOSFET, and the drain terminal of the low-side MOSFET. |
13 | CBOOT | P | High-side driver supply for bootstrap gate drive. |
14 | BIAS | P | Optional supply voltage input source for VCC regulator. This input takes over if VBIAS > 9V (typical). |
15 | PGOOD | O | Power-good pin. An open-collector output that goes low if VOUT is outside the specified regulation window. |
16 | FPWM/SYNC | I | Connect FPWM/SYNC to VCC to enable forced PWM (FPWM) mode with continuous conduction at light loads. Connect FPWM/SYNC to AGND to operate the LM5190 in diode emulation mode. FPWM/SYNC can also be used as a synchronization input to synchronize the internal oscillator to an external clock signal. |
17 | EN | I | An active-high precision input with rising threshold of 1V and hysteresis voltage of 100mV. If the EN voltage is less than 0.55V, the LM5190 is in shutdown mode. |
18 | ISNS+ | I | Current sense amplifier input. Connect this pin to the inductor side of the external current sense resistor using a low-current Kelvin connection. |
19 | VOUT | I | Output voltage sense and the current sense amplifier input. Connect VOUT to the output side of the current sense resistor. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Input voltage | VIN to AGND | –0.3 | 85 | V |
Input voltage | SW to AGND | –0.3 | 85 | V |
Input voltage | SW to AGND, transient < 20ns | –5 | V | |
Input voltage | CBOOT to SW | –0.3 | 10 | V |
Input voltage | CBOOT to AGND | –0.3 | 93 | V |
Input voltage | EN to AGND | –0.3 | 85 | V |
Input voltage | BIAS to AGND | -0.3 | 30 | V |
Input voltage | VCC, FB, PGOOD, FPWM/SYNC, RT to AGND | -0.3 | 8 | V |
Input voltage | ISET, IMON/ILIM to AGND | –0.3 | 5.5 | V |
Input voltage | VOUT, ISNS+ to AGND | –0.3 | 85 | V |
Input voltage | VOUT to ISNS+ | –0.3 | 0.3 | V |
Output voltage | HO to SW, transient < 20ns | –5 | V | |
Output voltage | LO to PGND, transient < 20ns | –1.5 | V | |
Operating junction temperature, TJ | –40 | 150 | °C | |
Storage temperature, Tstg | –55 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) | ±2000 | V |
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002 (2) | ±750 |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
VIN | Input supply voltage range | 5 | 80 | V | ||
VOUT | Output voltage range | 0.8 | 79 | V | ||
Pin Voltage | PGOOD, FB, FPWM/SYNC, RT | 0 | 8 | V | ||
Pin Voltage | COMP, ISET, IMON | 0 | 5.25 | V | ||
Pin Voltage | EN | 0 | 80 | V | ||
Pin Voltage | BIAS | 0 | 28 | V | ||
Pin Voltage | VOUT, ISNS+ | 0 | 79 | V | ||
TJ | Operating junction temperature | –40 | 150 | °C |
THERMAL METRIC(1) | LM5190 | UNIT | |
---|---|---|---|
RGY (VQFN) | |||
19 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 44.8 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 40.1 | °C/W |
RθJB | Junction-to-board thermal resistance | 21.1 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.9 | °C/W |
ψJB | Junction-to-board characterization parameter | 21.0 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 6.0 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
SUPPLY (VIN) | ||||||
IQ-SD | VIN shutdown current | VEN = 0V | 2.3 | 4.5 | µA | |
IQ-SBY | VIN standby current | Non-switching, 0.5V ≤ VEN ≤ 1V | 100 | µA | ||
ISLEEP1 | Sleep current, 5V | VIN = 24V, VVOUT = VBIAS = 5V, in sleep mode, VFPWM/SYNC = AGND, ISET floating | 15 | 30 | µA | |
ISLEEP2 | Sleep current, 12V | VIN = 24V, VVOUT = VBIAS = 12V, in sleep mode, VFPWM/SYNC = AGND, ISET floating | 20 | 35 | µA | |
ENABLE (EN) | ||||||
VSBY-TH | Shutdown-to-standby threshold | VEN rising | 0.55 | V | ||
VEN-TH | Enable voltage rising threshold | VEN rising, enable switching | 0.95 | 1.0 | 1.05 | V |
VEN-HYS | Enable hysteresis voltage | 100 | mV | |||
INTERNAL LDO (VCC) | ||||||
VVCC-REG | VCC regulation voltage | IVCC = 0mA to 110mA | 7.125 | 7.5 | 7.875 | V |
VVCC-UVLO | VCC UVLO rising threshold | 4.65 | 4.8 | 4.95 | V | |
VVCC-HYS | VCC UVLO hysteresis | 425 | mV | |||
IVCC-LIM | Internal LDO short-circuit current limit | 220 | mA | |||
EXTERNAL BIAS (BIAS) | ||||||
VBIAS-TH | VIN to VBIAS switchover rising threshold | 8.55 | 9 | 9.45 | V | |
VBIAS-HYS | VIN to VBIAS switchover hysteresis | 400 | mV | |||
REFERENCE VOLTAGE | ||||||
VREF-V | Regulated FB voltage | VIMON = 0V | 792 | 800 | 808 | mV |
VREF-I | Current loop reference voltage | VFB = 0V | 0.99 | 1 | 1.01 | V |
OUTPUT VOLTAGE (VOUT) | ||||||
VOUT-5V | 5V output voltage setpoint | FB tied to AGND | 4.95 | 5.0 | 5.05 | V |
VOUT-12V | 12V output voltage setpoint | FB tied to VCC, VIN = 24V | 11.88 | 12 | 12.12 | V |
ERROR AMPLIFIER (COMP) | ||||||
gm-VEA | Voltage loop EA transconductance | ΔVFB = 100mV | 1000 | µS | ||
gm-IEA | Current loop EA transconductance | ΔVIMON = 100mV | 1000 | µS | ||
IFB | Error amplifier input bias current | 75 | nA | |||
ICOMP-SRC | EA source current | VCOMP = 1V | 120 | µA | ||
ICOMP-SINK | EA sink current | VCOMP = 1V | 120 | µA | ||
OUTPUT CURRENT MONITOR (IMON/ILIM) | ||||||
gm-IMON | Monitor amplifier gain from VCS | VCS = 40mV | 1.94 | 2 | 2.06 | µA/mV |
IOFFSET | Monitor amplifier offset current | VCS = 0mV | 22.5 | 25 | 27.5 | µA |
CURRENT SETTING (ISET) | ||||||
IISET | ISET source current | 9 | 10 | 11 | µA | |
FORCED PWM MODE (FPWM/SYNC) | ||||||
VZC-SW | Zero-cross threshold | SW-PGND threshold | –5.5 | mV | ||
SWITCHING FREQUENCY | ||||||
VRT | RT pin regulation voltage | 10kΩ < RRT < 242kΩ | 1 | V | ||
FSW1 | Switching frequency 1 | VIN = 12V, RRT = 242kΩ to AGND | 90 | 100 | 110 | kHz |
FSW2 | Switching frequency 2 | VIN = 12V, RRT = 10kΩ to AGND | 2.0 | 2.2 | 2.4 | MHz |
VSLOPE | Slope compensation ramp amplitude | Referenced to ISNS+ to VOUT input | 45 | mV | ||
tON-MIN | Minimum on-time | 26 | 50 | ns | ||
tOFF-MIN | Minimum off-time | 80 | 125 | ns | ||
POWER GOOD (PGOOD) | ||||||
VPG-UV | Power-Good UV trip level | Falling with respect to the regulated voltage | 90% | 92% | 94% | |
VPG-OV | Power-Good OV trip level | Rising with respect to the regulated voltage | 108% | 110% | 112% | |
VPG-UV-HYST | Power-Good UV hysteresis | 3.7% | ||||
VPG-OV-HYST | Power-Good OV hysteresis | 3.7% | ||||
VPG-OL | PG voltage | Open collector, IPG = 4mA | 0.8 | V | ||
OVERVOLTAGE PROTECTION | ||||||
VOVTH-RISING | Overvoltage threshold | Rising with respect to regulated voltage | 108% | 110% | 112% | |
VOVTH-HYST | Overvoltage threshold hysteresis | 3.7% | ||||
STARTUP (Soft Start) | ||||||
tSS-INT | Internal fixed soft-start time | 1.9 | 2.75 | 3.8 | ms | |
BOOT CIRCUIT | ||||||
VBOOT-DROP | Internal diode forward drop | ICBOOT = 20mA, VCC to CBOOT | 0.8 | 1 | V | |
IBOOT | CBOOT to SW quiescent current, not switching | VEN = 5V, VCBOOT-SW = 7.5V | 25 | µA | ||
VBOOT-SW-UV-F | CBOOT to SW UVLO falling threshold | VCBOOT-SW falling | 2.75 | 3.1 | 3.75 | V |
VBOOT-SW-UV-HYS | CBOOT to SW UVLO hysteresis | 0.3 | V | |||
HIGH-SIDE GATE DRIVER (HO) | ||||||
VHO-HIGH | HO high-state output voltage | IHO = –100mA, VHO-HIGH = VCBOOT – VHO | 300 | mV | ||
VHO-LOW | HO low-state output voltage | IHO = 100mA | 75 | mV | ||
tHO-RISE | HO rise time (10% to 90%) | CLOAD = 2.7nF | 20 | ns | ||
tHO-FALL | HO fall time (90% to 10%) | CLOAD = 2.7nF | 8 | ns | ||
LOW-SIDE GATE DRIVER (LO) | ||||||
VLO-HIGH | LO high-state output voltage | ILO = –100mA | 300 | mV | ||
VLO-LOW | LO low-state output voltage | ILO = 100mA | 75 | mV | ||
tLO-RISE | LO rise time (10% to 90%) | CLOAD = 2.7nF | 20 | ns | ||
tLO-FALL | LO fall time (90% to 10%) | CLOAD = 2.7nF | 8 | ns | ||
ADAPTIVE DEADTIME CONTROL | ||||||
tDEAD1 | HO off to LO on deadtime | 21 | ns | |||
tDEAD2 | LO off to HO on deadtime | 21 | ns | |||
OVERCURRENT PROTECTION | ||||||
VCS-TH | Current limit threshold | Measured from ISNS+ to VOUT | 54 | 60 | 68 | mV |
VCS-TH-MIN | Minimum peak current limit threshold | Measured from ISNS+ to VOUT | 12 | mV | ||
ACS | CS amplifier gain | 9.5 | 10 | 10.6 | V/V | |
VCS-NEG | CS negative voltage threshold | –30 | mV | |||
THERMAL SHUTDOWN | ||||||
TJ-SD | Thermal shutdown threshold (1) | Temperature rising | 175 | °C | ||
TJ-HYS | Thermal shutdown hysteresis (1) | 15 | °C |
VIN = 12V, unless otherwise specified
VEN = 0V |
VIN = 24V | VVOUT = 12V |
VIN = 24V |
RRT = 10kΩ |
VIN = 24V | VVOUT = 5V |
The LM5190 is a switching DC/DC controller that features all of the functions necessary to implement a high-efficiency constant-current constant-voltage synchronous buck regulator operating over a wide input voltage range from 5V to 80V. The LM5190 is configured to provide a fixed 5V or 12V output, or an adjustable output from 0.8V to 79V. This easy-to-use controller integrates high-side and low-side MOSFET gate drivers capable of sourcing and sinking peak currents of 1.5A and 2.5A, respectively. Adaptive dead-time control is designed to minimize body diode conduction during switching transitions.
The current-mode control architecture using a shunt resistor current sensing provides inherent line feedforward, cycle-by-cycle peak current limiting, and easy loop compensation. Current-mode control also supports a wide duty cycle range for high input voltage and low-dropout applications as well as when application require a high step-down conversion ratio (for example, 10-to-1). The oscillator frequency is user-programmable between 100kHz to 2.2MHz, and the frequency can be synchronized as high as 2.5MHz by applying an external clock to the FPWM/SYNC pin.
An external bias supply can be connected to BIAS to maximize efficiency in high input voltage applications. A user-selectable diode emulation feature enables discontinuous conduction mode (DCM) operation to further improve efficiency and reduce power dissipation during light-load conditions. Fault protection features include current limiting, hiccup mode over-load protection, thermal shutdown, UVLO, and remote shutdown capability.
The LM5190 incorporates features to simplify the compliance with various EMI standards, for example CISPR 11 and CISPR 32 Class B requirements. DRSS techniques reduce the peak harmonic EMI signature.
The LM5190 is provided in a custom 19-pin VQFN package with an exposed pad to aid in thermal dissipation.