SNVSAA7B December   2015  – July 2021 LM53625-Q1 , LM53635-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 System Characteristics
    7. 7.7 Timing Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
      1. 8.2.1 Control Scheme
    3. 8.3 Feature Description
      1. 8.3.1 RESET Flag Output
      2. 8.3.2 Enable and Start-Up
      3. 8.3.3 Soft-Start Function
      4. 8.3.4 Current Limit
      5. 8.3.5 Hiccup Mode
      6. 8.3.6 Synchronizing Input
      7. 8.3.7 Undervoltage Lockout (UVLO) and Thermal Shutdown (TSD)
      8. 8.3.8 Input Supply Current
    4. 8.4 Device Functional Modes
      1. 8.4.1 AUTO Mode
      2. 8.4.2 FPWM Mode
      3. 8.4.3 Dropout
      4. 8.4.4 Input Voltage Frequency Foldback
    5. 8.5 Spread-Spectrum Operation
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 General Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 External Components Selection
            1. 9.2.1.2.1.1 Input Capacitors
              1. 9.2.1.2.1.1.1 Input Capacitor Selection
            2. 9.2.1.2.1.2 Output Inductors and Capacitors Selection
              1. 9.2.1.2.1.2.1 Inductor Selection
              2. 9.2.1.2.1.2.2 Output Capacitor Selection
          2. 9.2.1.2.2 Setting the Output Voltage
            1. 9.2.1.2.2.1 FB for Adjustable Versions
          3. 9.2.1.2.3 VCC
          4. 9.2.1.2.4 BIAS
          5. 9.2.1.2.5 CBOOT
          6. 9.2.1.2.6 Maximum Ambient Temperature
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Fixed 5-V Output for USB-Type Applications
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Fixed 3.3-V Output
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curves
      4. 9.2.4 Adjustable Output
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
        3. 9.2.4.3 Application Curves
    3. 9.3 What to Do and What Not to Do
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RNL|22
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.4.1 AUTO Mode

In AUTO mode the device moves between PWM and PFM as the load changes. At light loads the regulator operates in PFM . At higher loads the mode changes to PWM. The load currents at which the mode changes can be found in the Section 9.2.2.3.

In PWM, the converter operates as a constant frequency, current mode, full synchronous converter using PWM to regulate the output voltage. While operating in this mode the output voltage is regulated by switching at a constant frequency and modulating the duty cycle to control the power to the load. This provides excellent line and load regulation and low output voltage ripple. When in PWM the converter synchronizes to any valid clock signal on the SYNC input (see Section 8.4.3 and Section 8.4.4 ).

In PFM the high side FET is turned on in a burst of one or more cycles to provide energy to the load. The frequency of these bursts is adjusted to regulate the output, while diode emulation is used to maximize efficiency (see the Glossary). This mode provides high light-load efficiency by reducing the amount of input supply current required to regulate the output voltage at small loads. This trades off very good light load efficiency for larger output voltage ripple and variable switching frequency. Also, a small increase in the output voltage occurs in PFM. The actual switching frequency and output voltage ripple will depend on the input voltage, output voltage, and load. Typical switching waveforms for PFM are shown in Figure 8-8. See the Section 9.2.2.3 for output voltage variation in AUTO mode. The SYNC input is ignored during PFM operation.

A unique feature of this device is that a minimum input voltage is required for the regulator to switch from PWM to PFM at light load. This feature is a consequence of the advanced architecture employed to provide high efficiency at light loads. Figure 8-9 and Figure 8-10 indicates typical values of input voltage required to switch modes at no load. Also, once the regulator switches to PFM, at light load, it remains in that mode if the input voltage is reduced.

GUID-CC25F595-F5CF-46A5-A33D-A3DB1D01CA80-low.gifFigure 8-8 Typical PFM Switching Waveforms
GUID-22064B50-73CB-4470-AED3-EB87B6C01672-low.gifFigure 8-10 Input Voltage for Mode Change — Fixed 3.3-V Output, 2.2-µH Inductor
GUID-9B4C1A69-4427-46AC-B023-8529C13D41E5-low.gifFigure 8-9 Input Voltage for Mode Change — Fixed 5-V Output, 2.2-µH Inductor

IQ_VIN is the current consumed by a converter utilizing a LM53635-Q1 or LM53625-Q1 device while regulating without a load. While operating without a load, the LM53635-Q1 or LM53625-Q1 is only powering itself. The device draws power from two sources, its VIN pin, IQ, and either its FB pin for fixed versions or BIAS pin for adjustable versions, IB. Since BIAS or FB is connected to the output of the circuit, the power consumed is converted from input power with an effective efficiency, ηeff, of approximately 80 %. Here, effective efficiency is the added input power needed when lightly loading the converter of the LM53625-Q1 and LM53635- Q1 devices and is divided by the corresponding additional load. This allows unloaded current to be calculated as follows:

Equation 2. GUID-5DECA310-AA5C-4A4F-AB68-39DA26C8649A-low.gif

where

  • IQ_VIN is the current consumed by the operating (switching) buck converter utilizing the LM53625-Q1 or LM53635-Q1 while unloaded.
  • IQ is the current drawn by the LM53625-Q1 or LM53635-Q1 from its VIN terminal. See IQ in Section 7.5.
  • IEN is current drawn by the LM53625-Q1 or LM53635-Q1 from its EN terminal. Include this current if EN is connected to VIN. See IEN in Section 7.5. Note that this current drops to a very low value if connected to a voltage less than 5 V.
  • IB is bias/feedback current drawn by the LM53625-Q1 or LM53635-Q1 while the Buck converter utilizing it is unloaded. See IB in Section 7.5.
  • Idiv is the current drawn by the feedback voltage divider used to set output voltage for adjustable devices. This current is zero for fixed output voltage devices.
  • ηeff is the light load efficiency of the Buck converter with IQ_VIN removed from the input current of the buck converter input current. 0.8 is a conservative value that can be used under normal operating conditions.
Note:

The EN pin consumes a few micro-amperes when tied to high; see IEN. Add IEN to IQ as shown in Equation 2 if EN is tied to VIN. If EN is tied to a voltage less than 5 V, virtually no current is consumed allowing EN to be used as an UVLO pin once a voltage divider is added.