SNVSAA7B December   2015  – July 2021 LM53625-Q1 , LM53635-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 System Characteristics
    7. 7.7 Timing Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
      1. 8.2.1 Control Scheme
    3. 8.3 Feature Description
      1. 8.3.1 RESET Flag Output
      2. 8.3.2 Enable and Start-Up
      3. 8.3.3 Soft-Start Function
      4. 8.3.4 Current Limit
      5. 8.3.5 Hiccup Mode
      6. 8.3.6 Synchronizing Input
      7. 8.3.7 Undervoltage Lockout (UVLO) and Thermal Shutdown (TSD)
      8. 8.3.8 Input Supply Current
    4. 8.4 Device Functional Modes
      1. 8.4.1 AUTO Mode
      2. 8.4.2 FPWM Mode
      3. 8.4.3 Dropout
      4. 8.4.4 Input Voltage Frequency Foldback
    5. 8.5 Spread-Spectrum Operation
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 General Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 External Components Selection
            1. 9.2.1.2.1.1 Input Capacitors
              1. 9.2.1.2.1.1.1 Input Capacitor Selection
            2. 9.2.1.2.1.2 Output Inductors and Capacitors Selection
              1. 9.2.1.2.1.2.1 Inductor Selection
              2. 9.2.1.2.1.2.2 Output Capacitor Selection
          2. 9.2.1.2.2 Setting the Output Voltage
            1. 9.2.1.2.2.1 FB for Adjustable Versions
          3. 9.2.1.2.3 VCC
          4. 9.2.1.2.4 BIAS
          5. 9.2.1.2.5 CBOOT
          6. 9.2.1.2.6 Maximum Ambient Temperature
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Fixed 5-V Output for USB-Type Applications
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Fixed 3.3-V Output
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curves
      4. 9.2.4 Adjustable Output
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
        3. 9.2.4.3 Application Curves
    3. 9.3 What to Do and What Not to Do
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RNL|22
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.1 General Application

Figure 9-1 shows a general application schematic. FPWM, SYNC and EN are digital inputs. RESET is an open-drain output. FB connection is different for the fixed output options and the adjustable option.

  • The FPWM pin can be connected to GND to enable light-load PFM operation. Select this option if current consumption at light load is critical. The pin can be connected to VCC or VIN for forced 2-MHz operation. Select this option if constant switching frequency is critical over the entire load range. The pin can also be driven by an external signal and can be toggled while the part is in operation (by an MCU for example.) Refer to the Section 7.5 and Section 8.4 for more details on the operation and signal requirements of the FPWM pin.
  • The SYNC pin can be used to control the switching frequency and the phase of the converter. If the function is not needed, tie the SYNC pin to GND or 3 V.
  • The RESET pin can be left floating if the function is not required. If the function is needed, the pin must be connected to a DC rail through a pullup resistor (100 kΩ is the typical recommended value). Check Section 7.5 and Section 8.3.1 for the details of the RESET-pin function.
  • If the device is a fixed-output version (3.3 V or 5 V output option), connect the FB pin directly to the output. In the case of an adjustable-output part, connect the output to the FB pin through a voltage divider. See Section 9.2.1.2 for details on component selection.
  • The BIAS pin can be connected directly to the output except in applications that can experience inductive shorts (such as cases with long leads on the output). In those cases, a 3 Ω or so is necessary between the output and the BIAS pin, and a small capacitor to GND is necessary close to the BIAS pin (CBIAS). Alternatively, a Schottky diode can be connected between the OUT and GND to limit the negative voltage that can arise on the output during inductive shorts. In addition, BIAS can also be connected to an external rail if necessary and if available. The typical current into the bias pin is 15 mA when the device is operating in PWM mode at 2.1 MHz.
  • Power components must be chosen carefully for proper operation of the converter. Section 9.2.1.2 discusses the details of the process of choosing the input capacitors, output capacitors, and inductor for the application.

GUID-9FB39E14-66A6-48E1-BE0B-D9F6CA1FCEEE-low.pngFigure 9-1 General Application Circuit