SNVSB70F May   2019  – June 2021 LM61460-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Characteristics
    7. 8.7 Systems Characteristics
    8. 8.8 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  EN/SYNC Uses for Enable and VIN UVLO
      2. 9.3.2  EN/SYNC Pin Uses for Synchronization
      3. 9.3.3  Clock Locking
      4. 9.3.4  Adjustable Switching Frequency
      5. 9.3.5  PGOOD Output Operation
      6. 9.3.6  Internal LDO, VCC UVLO, and BIAS Input
      7. 9.3.7  Bootstrap Voltage and VCBOOT-UVLO (CBOOT Pin)
      8. 9.3.8  Adjustable SW Node Slew Rate
      9. 9.3.9  Spread Spectrum
      10. 9.3.10 Soft Start and Recovery From Dropout
      11. 9.3.11 Output Voltage Setting
      12. 9.3.12 Overcurrent and Short Circuit Protection
      13. 9.3.13 Thermal Shutdown
      14. 9.3.14 Input Supply Current
    4. 9.4 Device Functional Modes
      1. 9.4.1 Shutdown Mode
      2. 9.4.2 Standby Mode
      3. 9.4.3 Active Mode
        1. 9.4.3.1 CCM Mode
        2. 9.4.3.2 Auto Mode - Light Load Operation
          1. 9.4.3.2.1 Diode Emulation
          2. 9.4.3.2.2 Frequency Reduction
        3. 9.4.3.3 FPWM Mode - Light Load Operation
        4. 9.4.3.4 Minimum On-time (High Input Voltage) Operation
        5. 9.4.3.5 Dropout
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1  Choosing the Switching Frequency
        2. 10.2.2.2  Setting the Output Voltage
        3. 10.2.2.3  Inductor Selection
        4. 10.2.2.4  Output Capacitor Selection
        5. 10.2.2.5  Input Capacitor Selection
        6. 10.2.2.6  BOOT Capacitor
        7. 10.2.2.7  BOOT Resistor
        8. 10.2.2.8  VCC
        9. 10.2.2.9  BIAS
        10. 10.2.2.10 CFF and RFF Selection
        11. 10.2.2.11 External UVLO
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Ground and Thermal Considerations
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.3.1 EN/SYNC Uses for Enable and VIN UVLO

Start-up and shutdown are controlled by the EN/SYNC input and VIN UVLO. For the device to remain in shutdown mode, apply a voltage below VEN_WAKE (0.4 V) to the EN pin. In shutdown mode, the quiescent current drops to 0.6 µA (typical). At a voltage above VEN_WAKE and below VEN, VCC is active and the SW node is inactive. Once the EN voltage is above VEN, the chip begins to switch normally, provided the input voltage is above 3 V.

The EN/SYNC pin cannot be left floating. The simplest way to enable the operation is to connect the EN/SYNC pin to VIN, allowing self-start-up of the LM61460-Q1 when VIN drives the internal VCC above its UVLO level. However, many applications benefit from the employment of an enable divider network as shown in Figure 9-1, which establishes a precision input undervoltage lockout (UVLO). This can be used for sequencing, preventing re-triggering of the device when used with long input cables, or reducing the occurrence of deep discharge of a battery power source. Note that the precision enable threshold, VEN, has a 8.1% tolerance. Hysteresis must be enough to prevent re-triggering. External logic output of another IC can also be used to drive the EN/SYNC pin, allowing system power sequencing.

GUID-1179D25A-F4B2-443D-8D45-45A0B93717A6-low.gifFigure 9-1 VIN UVLO Using the EN pin

Resistor values can be calculated using Equation 1. See Section 10.2.2.11 for additional information.

Equation 1. GUID-A4C3B0F8-1D41-4FCC-B63D-87C2D5FE5E33-low.gif

where

  • VON is the desired typical start-up input voltage for the circuit being designed

Note that since the EN/SYNC pin can also be used as an external synchronization clock input. A blanking time, tB, is applied to the enable logic after a clock edge is detected. Any logic change within the blanking time is ignored. Blanking time is not applied when the device is in shutdown mode. The blanking time ranges from 4 µs to 28 µs. To effectively disable the output, the EN/SYNC input must stay low for longer than 28 µs.