SNVSBD5D May   2019  – July 2022 LM61460

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2.     ESD Ratings
    3. 7.2 Recommended Operating Conditions
    4. 7.3 Thermal Information
    5. 7.4 Electrical Characteristics
    6. 7.5 Timing Characteristics
    7. 7.6 Systems Characteristics
    8. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  EN/SYNC Uses for Enable and VIN UVLO
      2. 8.3.2  EN/SYNC Pin Uses for Synchronization
      3. 8.3.3  Clock Locking
      4. 8.3.4  Adjustable Switching Frequency
      5. 8.3.5  PGOOD Output Operation
      6. 8.3.6  Internal LDO, VCC UVLO, and BIAS Input
      7. 8.3.7  Bootstrap Voltage and VCBOOT-UVLO (CBOOT Pin)
      8. 8.3.8  Adjustable SW Node Slew Rate
      9. 8.3.9  Spread Spectrum
      10. 8.3.10 Soft Start and Recovery From Dropout
      11. 8.3.11 Output Voltage Setting
      12. 8.3.12 Overcurrent and Short Circuit Protection
      13. 8.3.13 Thermal Shutdown
      14. 8.3.14 Input Supply Current
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Active Mode
        1. 8.4.3.1 CCM Mode
        2. 8.4.3.2 Auto Mode – Light-Load Operation
          1. 8.4.3.2.1 Diode Emulation
          2. 8.4.3.2.2 Frequency Reduction
        3. 8.4.3.3 FPWM Mode – Light-Load Operation
        4. 8.4.3.4 Minimum On-Time (High Input Voltage) Operation
        5. 8.4.3.5 Dropout
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Choosing the Switching Frequency
        2. 9.2.2.2  Setting the Output Voltage
        3. 9.2.2.3  Inductor Selection
        4. 9.2.2.4  Output Capacitor Selection
        5. 9.2.2.5  Input Capacitor Selection
        6. 9.2.2.6  BOOT Capacitor
        7. 9.2.2.7  BOOT Resistor
        8. 9.2.2.8  VCC
        9. 9.2.2.9  BIAS
        10. 9.2.2.10 CFF and RFF Selection
        11. 9.2.2.11 External UVLO
      3. 9.2.3 Application Curves
      4. 9.2.4 USB Type-C System Example
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
        3. 9.2.4.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Ground and Thermal Considerations
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4 Electrical Characteristics

Limits apply over the recommended operating junction temperature range of -40°C to +150°C, unless otherwise stated. Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: VIN = 13.5 V.  VIN1 shorted to VIN2 = VIN.  VOUT is converter output voltage.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE AND CURRENT
VIN_OPERATE Input operating voltage(2) Needed to start up 3.95 V
Once operating 3.0
VIN_OPERATE_H Hysteresis(2) 1 V
IQ_VIN Operating quiescent current (not switching) VFB = +5%, VBIAS = 5 V 9 18 µA
ISD Shutdown quiescent current; measured at the VIN pin EN = 0 V, TJ  = 25℃ 0.6 6 µA
ENABLE
VEN Enable input threshold voltage – rising 1.263 V
VEN-ACC Enable input threshold voltage – rising deviation from typical –5%  5%
VEN-HYST Enable threshold hysteresis as percentage of VEN  (typical) 24% 28% 32%
VEN-WAKE Enable wake-up threshold 0.4 V
IEN Enable pin input current VIN = EN = 13.5 V 2.3 nA 
VEN_SYNC Edge height necessary to sync using EN/SYNC pin Rise/fall time < 30 ns 2.4 V
LDO - VCC
VCC Internal VCC voltage VBIAS > 3.4  V, CCM operation(2) 3.3 V
VBIAS = 3.1 V, non-switching 3.1
VCC_UVLO Internal VCC input undervoltage lockout VCC rising undervoltage threshold 3.6 V
VCC_UVLO_HYST Internal VCC input undervoltage lockout Hysteresis below VCC_UVLO 1.1 V
FEEDBACK
VFB_acc Initial reference voltage accuracy VIN = 3.3 V to 36 V, FPWM mode –1% 1%
IFB Input current from FB to AGND  Adjustable versions only, FB = 1 V 10 nA
OSCILLATOR
fADJ Minimum adjustable frequency by RT or SYNC RT = 66.5 kΩ 0.18 0.2 0.22 MHz
Adjustable frequency by RT or SYNC with 400-kHz setting RT = 33.2 kΩ  0.36 0.4 0.44 MHz
Maximum adjustable frequency by RT or SYNC RT = 5.76 kΩ 1.98 2.2 2.42 MHz
MOSFETS
RDS(ON)_HS Power switch on-resistance High-side MOSFET RDS(ON) 41 82 mΩ
RDS(ON)_LS Power switch on-resistance Low-side MOSFET RDS(ON) 21 45 mΩ
VBOOT_UVLO Voltage on CBOOT pin compared to SW which will turn off high-side switch 2.1 V
CURRENT LIMITS
IL-HS High-side switch current limit(1) Duty cycle approaches 0% 8.9 10.3 11.5 A
IL-LS Low-side switch current limit 6.1 7.1 8.1 A
IL-ZC Zero-cross current limit.  Positive  current direction is out of the SW pin Auto mode, static measurement 0.25 A
IL-NEG Negative current limit FPWM and SYNC Modes.  Positive current direction is out of SW pin. FPWM operation –3 A
IPK_MIN_0 Minimum peak command in auto mode and device current rating Pulse duration < 100 ns 25%
IPK_MIN_100 Minimum peak command in auto mode and device current rating Pulse duration > 1 µs 12.5%
VHICCUP Ratio of FB voltage to in-regulation FB voltage Not during soft start 40%
POWER GOOD
PGDOV PGOOD upper threshold – rising % of VOUT setting 105% 107% 110%
PGDUV PGOOD lower threshold – falling % of VOUT setting 92% 94% 96.5%
PGDHYST PGOOD upper threshold (rising and falling) % of VOUT setting 1.3%
VIN(PGD_VALID) Input voltage for proper PGOOD function 1.0 V
VPGD(LOW) Low level PGOOD function output voltage 46-µA pullup to the PGOOD pin, VIN = 1.0 V, EN = 0 V 0.4 V
1-mA pullup to the PGOOD pin, VIN = 13.5 V, EN = 0 V 0.4
2-mA pullup to the PGOOD pin, VIN = 13.5 V, EN = 3.3 V 0.4
RPGD RDS(ON) of PGOOD output 1-mA pullup to PGOOD pin, EN = 0 V 17 40 Ω
1-mA pullup to PGOOD pin, EN = 3.3 V 40 90 Ω
IOV Pulldown current at the SW node under overvoltage condition 0.5 mA
THERMAL SHUTDOWN
TSD_R Thermal shutdown rising threshold(2) 158 168 180 ℃
TSD_HYST Thermal shutdown hysteresis(2) 10 ℃
(1) High-side current limit is function of duty factor. High-side current limit is highest at small duty factor and less at higher duty factors.
(2) Parameter specified by design, statistical analysis and production testing of correlated parameters.