SNVSBA0D February   2020  – August 2021 LM61480-Q1 , LM61495-Q1 , LM62460-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Characteristics
    7. 7.7 Switching Characteristics
    8. 7.8 System Characteristics
    9. 7.9 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Output Voltage Selection
      2. 8.3.2  Enable EN Pin and Use as VIN UVLO
      3. 8.3.3  SYNC/MODE Uses for Synchronization
      4. 8.3.4  Clock Locking
      5. 8.3.5  Adjustable Switching Frequency
      6. 8.3.6  RESET Output Operation
      7. 8.3.7  Internal LDO, VCC UVLO, and BIAS Input
      8. 8.3.8  Bootstrap Voltage and VCBOOT-UVLO (CBOOT Pin)
      9. 8.3.9  Adjustable SW Node Slew Rate
      10. 8.3.10 Spread Spectrum
      11. 8.3.11 Soft Start and Recovery From Dropout
      12. 8.3.12 Overcurrent and Short Circuit Protection
      13. 8.3.13 Hiccup
      14. 8.3.14 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Active Mode
        1. 8.4.3.1 Peak Current Mode Operation
        2. 8.4.3.2 Auto Mode Operation
          1. 8.4.3.2.1 Diode Emulation
        3. 8.4.3.3 FPWM Mode Operation
        4. 8.4.3.4 Minimum On-time (High Input Voltage) Operation
        5. 8.4.3.5 Dropout
        6. 8.4.3.6 Recovery from Dropout
        7. 8.4.3.7 Other Fault Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Choosing the Switching Frequency
        2. 9.2.2.2  Setting the Output Voltage
        3. 9.2.2.3  Inductor Selection
        4. 9.2.2.4  Output Capacitor Selection
        5. 9.2.2.5  Input Capacitor Selection
        6. 9.2.2.6  BOOT Capacitor
        7. 9.2.2.7  BOOT Resistor
        8. 9.2.2.8  VCC
        9. 9.2.2.9  CFF and RFF Selection
        10. 9.2.2.10 RSPSP Selection
        11. 9.2.2.11 RT Selection
        12. 9.2.2.12 RMODE Selection
        13. 9.2.2.13 External UVLO
        14. 9.2.2.14 Maximum Ambient Temperature
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Ground and Thermal Considerations
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Glossary
    6. 12.6 Electrostatic Discharge Caution
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.2.5 Input Capacitor Selection

The ceramic input capacitors provide a low impedance source to the regulator in addition to supplying the ripple current and isolating switching noise from other circuits. A minimum of 10-μF ceramic capacitance is required on the input of the LM6x4xx-Q1. Use 2 x 10-μF ceramic capacitance or more for better EMI performance. This must be rated for at least the maximum input voltage that the application requires. It is preferable to have twice the maximum input voltage to reduce DC bias derating. This capacitance can be increased to help reduce input voltage ripple and maintain the input voltage during load transients. In addition, a small case size (0603 or 0402) ceramic capacitor must be used at each input/ground pin pair, VIN1/PGND1 and VIN2/PGND2, immediately adjacent to the regulator. The capacitor should have a voltage rating of at least double the maximum input voltage to minimize derating. The capacitor must also have an X7R or better dielectric. Choose the highest capacitor value with these parameters. This provides a high frequency bypass to reduce switch-node ring and electromagnetic interference emissions. The QFN (RJR) package provides two input voltage pins and two power ground pins on opposite sides of the package. This allows the input capacitors to be split and placed optimally with respect to the internal power MOSFETs, thus improving the effectiveness of the input bypassing. This example places two 10-μF, 50-V, 1206, X7R ceramic capacitors and two 0.47-μF, 50-V, 0603, X7R ceramic capacitors at each VIN/PGND pin pair.

Often, it is desirable to use an electrolytic capacitor on the input in parallel with the ceramics. This is especially true if long leads/traces are used to connect the input supply to the regulator. The moderate ESR of this capacitor can help dampen ringing on the input supply caused by the inductance of the long power leads. The use of this additional capacitor also helps with momentary voltage dips caused by input supplies with unusually high impedance.

Most of the input switching current passes through the ceramic input capacitors. The approximate worst case RMS value of this current can be calculated with Equation 7. This value must be checked against the manufacturers' maximum ratings.

Equation 7. GUID-D24DF668-D322-44EF-B104-8C20D3C0D591-low.gif