SNVSCR9A October   2024  – December 2024 LM61480T-Q1 , LM61495T-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Output Voltage Selection
      2. 7.3.2  Enable EN Pin and Use as VIN UVLO
      3. 7.3.3  SYNC/MODE Uses for Synchronization
      4. 7.3.4  Clock Locking
      5. 7.3.5  Adjustable Switching Frequency
      6. 7.3.6  RESET Output Operation
      7. 7.3.7  Internal LDO, VCC UVLO, and BIAS Input
      8. 7.3.8  Bootstrap Voltage and VCBOOT-UVLO (CBOOT Pin)
      9. 7.3.9  Adjustable SW Node Slew Rate
      10. 7.3.10 Spread Spectrum
      11. 7.3.11 Soft Start and Recovery From Dropout
      12. 7.3.12 Overcurrent and Short-Circuit Protection
      13. 7.3.13 Hiccup
      14. 7.3.14 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Active Mode
        1. 7.4.3.1 Peak Current Mode Operation
        2. 7.4.3.2 Auto Mode Operation
          1. 7.4.3.2.1 Diode Emulation
        3. 7.4.3.3 FPWM Mode Operation
        4. 7.4.3.4 Minimum On-time (High Input Voltage) Operation
        5. 7.4.3.5 Dropout
        6. 7.4.3.6 Recovery from Dropout
        7. 7.4.3.7 Other Fault Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Choosing the Switching Frequency
        2. 8.2.2.2  Setting the Output Voltage
        3. 8.2.2.3  Inductor Selection
        4. 8.2.2.4  Output Capacitor Selection
        5. 8.2.2.5  Input Capacitor Selection
        6. 8.2.2.6  BOOT Capacitor
        7. 8.2.2.7  BOOT Resistor
        8. 8.2.2.8  VCC
        9. 8.2.2.9  CFF and RFF Selection
        10. 8.2.2.10 RSPSP Selection
        11. 8.2.2.11 RT Selection
        12. 8.2.2.12 RMODE Selection
        13. 8.2.2.13 External UVLO
        14. 8.2.2.14 Maximum Ambient Temperature
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Ground and Thermal Considerations
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Glossary
    7. 9.7 Electrostatic Discharge Caution
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.9 Adjustable SW Node Slew Rate

To allow optimization of EMI with respect to efficiency, the LM614xxT-Q1 is designed to allow a resistor to select the strength of the high-side FET driver during turn-on. See Figure 7-10. The current drawn through the RBOOT pin (the dotted loop) is magnified and drawn through from CBOOT (the dashed line). This current is used to turn on the high-side power MOSEFT.

LM61480T-Q1 LM61495T-Q1 Simplified Circuit Showing How RBOOT Functions Figure 7-10 Simplified Circuit Showing How RBOOT Functions

Rise time is rapid with RBOOT short circuited to CBOOT. In this condition, the SW node harmonics roll off at –20dBµV per decade until around 150MHz where the harmonics begin rolling off at –40dBµV per decade. Slowing the rise time decreases the frequency where this transition occurs which provides more rolloff in the higher frequencies which provides more margin on EMI scans. If CBOOT and RBOOT are connected through 700Ω, slew time due to high-side turnon is limited to no more than 13ns. 10ns is typical when converting 13.5V to 5V. This slow rise time allows energy in SW node harmonics to roll off near 50MHz under most conditions. Rolling off harmonics eliminates the need for shielding and common mode chokes in many applications. Note that rise time increases with increasing input voltage. Noise due to stored charge is also greatly reduced with higher RBOOT resistance. Switching with a slower slew rate decreases efficiency. Take care to optimize the resistance to provide the best EMI while not generating too much heat. If RBOOT is left open, rise time is set to the maximum value.