SNVSCR9A October   2024  – December 2024 LM61480T-Q1 , LM61495T-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Output Voltage Selection
      2. 7.3.2  Enable EN Pin and Use as VIN UVLO
      3. 7.3.3  SYNC/MODE Uses for Synchronization
      4. 7.3.4  Clock Locking
      5. 7.3.5  Adjustable Switching Frequency
      6. 7.3.6  RESET Output Operation
      7. 7.3.7  Internal LDO, VCC UVLO, and BIAS Input
      8. 7.3.8  Bootstrap Voltage and VCBOOT-UVLO (CBOOT Pin)
      9. 7.3.9  Adjustable SW Node Slew Rate
      10. 7.3.10 Spread Spectrum
      11. 7.3.11 Soft Start and Recovery From Dropout
      12. 7.3.12 Overcurrent and Short-Circuit Protection
      13. 7.3.13 Hiccup
      14. 7.3.14 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Active Mode
        1. 7.4.3.1 Peak Current Mode Operation
        2. 7.4.3.2 Auto Mode Operation
          1. 7.4.3.2.1 Diode Emulation
        3. 7.4.3.3 FPWM Mode Operation
        4. 7.4.3.4 Minimum On-time (High Input Voltage) Operation
        5. 7.4.3.5 Dropout
        6. 7.4.3.6 Recovery from Dropout
        7. 7.4.3.7 Other Fault Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Choosing the Switching Frequency
        2. 8.2.2.2  Setting the Output Voltage
        3. 8.2.2.3  Inductor Selection
        4. 8.2.2.4  Output Capacitor Selection
        5. 8.2.2.5  Input Capacitor Selection
        6. 8.2.2.6  BOOT Capacitor
        7. 8.2.2.7  BOOT Resistor
        8. 8.2.2.8  VCC
        9. 8.2.2.9  CFF and RFF Selection
        10. 8.2.2.10 RSPSP Selection
        11. 8.2.2.11 RT Selection
        12. 8.2.2.12 RMODE Selection
        13. 8.2.2.13 External UVLO
        14. 8.2.2.14 Maximum Ambient Temperature
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Ground and Thermal Considerations
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Glossary
    7. 9.7 Electrostatic Discharge Caution
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.10 Spread Spectrum

Spread spectrum is configurable using the SPSP pin. Spread spectrum eliminates peak emissions at specific frequencies by spreading these peaks across a wider range of frequencies than a part with fixed-frequency operation. The LM614xxT-Q1 implements a modulation pattern designed to reduce low frequency-conducted emissions from the first few harmonics of the switching frequency. The pattern can also help reduce the higher harmonics that are more difficult to filter, which can fall in the FM band. These harmonics often couple to the environment through electric fields around the switch node and inductor. The LM614xxT-Q1 uses a ±4% (typical) spread of frequencies which can spread energy smoothly across the FM and TV bands. The device implements Dual Random Spread Spectrum (DRSS). DRSS is a combination of a triangular frequency spreading pattern and pseudorandom frequency hopping. The combination allows the spread spectrum to be very effective at spreading the energy at the following:

  • Fundamental switching harmonic with slow triangular pattern
  • High frequency harmonics with additional psuedorandom jumps at the switching frequency
The advantage of DRSS is the equivalent harmonic attenuation in the upper frequencies with a smaller fundamental frequency deviation. This feature reduces the amount of input current and output voltage ripple that is introduced at the modulating frequency. Additionally, the LM614xxT-Q1 also allows you to further reduce the output voltage ripple caused by the spread spectrum modulating pattern. With the SPSP pin grounded, the spread spectrum is disabled. With the SPSP pin tied to VCC, the spread spectrum is on. With the SPSP pin tied through a resistor to ground, the spread spectrum is on. Also, a modulating tone correction is applied to the switcher to reduce the output voltage ripple caused by the frequency modulation. The resistor is usually around 20kΩ, and can be more precisely calculated using Equation 4.

Equation 4. R S P S P k Ω = 14.17 × V I N V O U T V I N - V O U T I R A T E D × L × f S W + 1.22
where IRATED is the DC current rating of the device, as mentioned in Recommended Operating Conditions.
LM61480T-Q1 LM61495T-Q1 Output Ripple Without Ripple Cancellation Showing VSW (Top), FSW (Middle), VOUT (Bottom) Figure 7-11 Output Ripple Without Ripple Cancellation Showing VSW (Top), FSW (Middle), VOUT (Bottom)
LM61480T-Q1 LM61495T-Q1 Output Ripple With Ripple Cancellation Showing VSW (Top), FSW (Middle), VOUT (Bottom) Figure 7-12 Output Ripple With Ripple Cancellation Showing VSW (Top), FSW (Middle), VOUT (Bottom)

The spread spectrum is only available while the clock of the LM614xxT-Q1 are free running at the natural frequency. Any of the following conditions overrides spread spectrum, turning spread spectrum off:

  • The clock is slowed due to operation at low input voltage. This action is operation in dropout.
  • The clock is slowed under light load in auto mode. This is normally not seen above 750mA load. Note that if the device is operating in FPWM mode, spread spectrum is active, even if there is no load.
  • The clock is slowed due to high input-to-output voltage ratio. This mode of operation is expected if on-time reaches minimum on-time. See the Timing Requirements.
  • The clock is synchronized with an external clock.