SNVSBP3B May   2020  – June 2021 LM62435-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Characteristics
    7. 7.7 Systems Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  EN Uses for Enable and VIN UVLO
      2. 8.3.2  MODE/SYNC Pin Operation
        1. 8.3.2.1 Level-Dependent MODE/SYNC Pin Control
        2. 8.3.2.2 Pulse-Dependent MODE/SYNC Pin Control
        3. 8.3.2.3 Clock Locking
      3. 8.3.3  PGOOD Output Operation
      4. 8.3.4  Internal LDO, VCC UVLO, and BIAS Input
      5. 8.3.5  Bootstrap Voltage and VCBOOT-UVLO (CBOOT Pin)
      6. 8.3.6  Adjustable SW Node Slew Rate
      7. 8.3.7  Spread Spectrum
      8. 8.3.8  Soft Start and Recovery From Dropout
      9. 8.3.9  Output Voltage Setting
      10. 8.3.10 Overcurrent and Short Circuit Protection
      11. 8.3.11 Thermal Shutdown
      12. 8.3.12 Input Supply Current
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Active Mode
        1. 8.4.3.1 CCM Mode
        2. 8.4.3.2 Auto Mode - Light Load Operation
          1. 8.4.3.2.1 Diode Emulation
          2. 8.4.3.2.2 Frequency Reduction
        3. 8.4.3.3 FPWM Mode - Light Load Operation
        4. 8.4.3.4 Minimum On-time (High Input Voltage) Operation
        5. 8.4.3.5 Dropout
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Choosing the Switching Frequency
        2. 9.2.2.2  Setting the Output Voltage
        3. 9.2.2.3  Inductor Selection
        4. 9.2.2.4  Output Capacitor Selection
        5. 9.2.2.5  Input Capacitor Selection
        6. 9.2.2.6  BOOT Capacitor
        7. 9.2.2.7  BOOT Resistor
        8. 9.2.2.8  VCC
        9. 9.2.2.9  BIAS
        10. 9.2.2.10 CFF and RFF Selection
        11. 9.2.2.11 External UVLO
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Ground and Thermal Considerations
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4 Thermal Information

The value of RθJA given in this table is only valid for comparison with other packages and cannot be used for design purposes. These values were calculated in accordance with JESD 51-7, and simulated on a 4-layer JEDEC board. They do not represent the performance obtained in an actual application. For example, with a 4-layer PCB, a RΘJA = 25℃/W can be achieved. For design information see Maximum Ambient Temperature versus Output Current.
THERMAL METRIC (1)(2) LM62435-Q1 UNIT
RJR (QFN)
14 PINS
RθJA Junction-to-ambient thermal resistance (LM61460-Q1 EVM)     25 °C/W
RθJA Junction-to-ambient thermal resistance (JESD 51-7) 58.7 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 26.1 °C/W
RθJB Junction-to-board thermal resistance 19.2 °C/W
ΨJT Junction-to-top characterization parameter 1.4 °C/W
ΨJB Junction-to-board characterization parameter 19 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance - °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
(2) The value of RθJA given in this table is only valid for comparison with other packages and cannot be used for design purposes. These values were calculated in accordance with JESD 51-7, and simulated on a 4-layer JEDEC board. They do not represent the performance obtained in an actual application.