SNVSBW1C December 2021 – August 2024 LM63440-Q1 , LM63460-Q1
PRODUCTION DATA
Because the output voltage is 5V in this design, connect the BIAS pin to VOUT to reduce the VCC LDO power loss. The output voltage is supplying the LDO current instead of the input voltage. The power saving is IVCC × (VIN – VOUT). The power saving is more significant when VIN is much higher than VOUT and at high switching frequencies. To prevent output voltage noise and transients from coupling to BIAS, add a series resistor between 1Ω and 10Ω between VOUT and BIAS. In addition, add a bypass capacitor with a value of 1μF or higher close to the BIAS pin to filter noise. Note the maximum allowed voltage on BIAS is 16V.