SNVSCO0 January   2024 LM63635C-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Characteristics
    7. 6.7 Switching Characteristics
    8. 6.8 System Characteristics
    9. 6.9 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Voltage Selection
      2. 7.3.2 Switching Frequency Selection
        1. 7.3.2.1 Spread Spectrum Option
      3. 7.3.3 Enable and Start-Up
      4. 7.3.4 RESET Flag Output
      5. 7.3.5 Undervoltage Lockout, Thermal Shutdown, and Output Discharge
    4. 7.4 Device Functional Modes
      1. 7.4.1 Overview
      2. 7.4.2 Light Load Operation
      3. 7.4.3 Dropout Operation
      4. 7.4.4 Minimum On-Time Operation
      5. 7.4.5 Current Limit and Short-Circuit Operation
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Choosing the Switching Frequency
        2. 8.2.2.2 Inductor Selection
        3. 8.2.2.3 Output Capacitor Selection
        4. 8.2.2.4 Input Capacitor Selection
        5. 8.2.2.5 CBOOT
        6. 8.2.2.6 VCC
        7. 8.2.2.7 External UVLO
        8. 8.2.2.8 Maximum Ambient Temperature
      3. 8.2.3 Application Curves
      4. 8.2.4 EMI Performance Curves
    3. 8.3 Best Design Practices
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
        1. 8.5.1.1 Ground and Thermal Considerations
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Device Nomenclature
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Glossary
    7. 9.7 Electrostatic Discharge Caution
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.4 RESET Flag Output

The RESET flag function (RESET output pin) of the LM63635C-Q1 device can be used to reset a system microprocessor whenever the output voltage is out of regulation. This open-drain output goes low under fault conditions, such as current limit and thermal shutdown, as well as during normal start-up. A glitch filter prevents false flag operation for short excursions of the output voltage, such as during line and load transients. Output voltage excursions lasting less than tdg do not trip the RESET flag. After the FB voltage has returned to the regulation value and after a delay of trise-delay, the RESET flag goes high. RESET operation can best be understood by reference to Figure 7-3 and Figure 7-4.

The RESET output consists of an open-drain NMOS, requiring an external pullup resistor to a logic supply that can be used. The RESET output can also be pulled up to either VCC or VOUT through an appropriate resistor, as desired. Pullup resistor values in the range of 10kΩ to 100kΩ are reasonable. If this function is not needed, the RESET pin can be left floating. When EN is pulled low, the flag output is also forced low. With EN low, RESET remains valid as long as the input voltage is ≥ 1.2V (typical). Limit the current into the RESET flag pin to approximately 5mA. The maximum current is internally limited to approximately 50mA when the device is enabled and approximately 65mA when the device is disabled. The internal current limit protects the device from any transient currents that can occur when discharging a filter capacitor connected to this output.

GUID-20240104-SS0I-CNB3-QSVN-TBW98ZQKGPRQ-low.svgFigure 7-3 Static RESET Operation
GUID-20240104-SS0I-RFFN-ZJ3J-RVR4VQG1GNZ0-low.svgFigure 7-4 RESET Timing Behavior