SNAS207B May   2004  – January 2024 LM64

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Operating Ratings
    3. 5.3 DC Electrical Characteristics
    4. 5.4 Operating Electrical Characteristics
    5. 5.5 AC Electrical Characteristics
    6. 5.6 Digital Electrical Characteristics
    7. 5.7 SMBus Logical Electrical Characteristics
    8. 5.8 SMBus Digital Switching Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Conversion Sequence
      2. 6.3.2  The ALERT Output
        1. 6.3.2.1 ALERT Output as a Temperature Comparator
        2. 6.3.2.2 ALERT Output as an Interrupt
        3. 6.3.2.3 ALERT Output as an SMBus ALERT
      3. 6.3.3  SMBus Interface
      4. 6.3.4  Power-On Reset (POR) Default States
      5. 6.3.5  Temperature Data Format
      6. 6.3.6  Open-Drain Outputs, Inputs, and Pull-Up Resistors
      7. 6.3.7  Diode Fault Detection
      8. 6.3.8  Communicating with the LM64
      9. 6.3.9  Digital Filter
      10. 6.3.10 Fault Queue
      11. 6.3.11 One-Shot Register
      12. 6.3.12 Serial Interface Reset
  8. 7 Registers
    1. 7.1 LM64 Registers
      1. 7.1.1 LM64 Register Map in Hexadecimal Order
      2. 7.1.2 LM64 Register Map in Functional Order
      3. 7.1.3 LM64 Initial Register Sequence and Register Descriptions in Functional Order
        1. 7.1.3.1 LM64 Required Initial Fan Control Register Sequence
      4. 7.1.4 LM64 Register Descriptions in Functional Order
        1. 7.1.4.1 Fan Control Registers
        2. 7.1.4.2 Configuration Register
        3. 7.1.4.3 Tachometer Count And Limit Registers
        4. 7.1.4.4 Local Temperature And Local High Setpoint Registers
        5. 7.1.4.5 Remote Diode Temperature, Offset And Setpoint Registers
        6. 7.1.4.6 ALERT Status And Mask Registers
        7. 7.1.4.7 Conversion Rate And One-Shot Registers
        8. 7.1.4.8 ID Registers
    2. 7.2 General Purpose Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Fan Control Duty Cycle VS. Register Settings and Frequency
        1. 8.1.1.1 Computing Duty Cycles for a Given Frequency
      2. 8.1.2 Use of the Lookup Table for Non-Linear PWM Values VS Temperature
      3. 8.1.3 NON-Ideality Factor and Temperature Accuracy
        1. 8.1.3.1 Diode Non_Ideality
        2. 8.1.3.2 Compensating for Diode Non-Ideality
      4. 8.1.4 Computing RPM of the Fan from the TACH Count
    2. 8.2 Typical Application
  10. 9 Layout
    1. 9.1 PCB Layout for Minimizing Noise
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.8 SMBus Digital Switching Characteristics

Unless otherwise noted, these specifications apply for VDD = +3.0 VDC to +3.6 VDC, CL (load capacitance) on output lines = 80 pF. Boldface limits apply for TA = TJ; TMIN ≤ TA ≤ TMAX; all other limits TA = TJ = +25°C, unless otherwise noted. The switching characteristics of the LM64 fully meet or exceed the published specifications of the SMBus version 2.0. The following parameters are the timing relationships between SMBCLK and SMBDAT signals related to the LM64. They adhere to but are not necessarily the same as the SMBus bus specifications.
SymbolParameterConditionsLimits
(1)		Units
(Limit)
fSMBSMBus Clock Frequency10
100		kHz (min)
kHz (max)
tLOWSMBus Clock Low TimeFrom VIN(0) max to VIN(0) max4.7µs (min)
tHIGHSMBus Clock High TimeFrom VIN(1) min to VIN(1) min4.0
50		µs (min)
µs (max)
tRSMBus Rise TimeSee (2)1µs (max)
tFSMBus Fall TimeSee (3)0.3µs (max)
tOFOutput Fall TimeCL = 400 pF, IO = 3 mA250ns (max)
tTIMEOUTSMBData and SMBCLK Time Low for Reset of Serial Interface See (4)25
35		ms (min)
ms (max)
tSU:DATData In Setup Time to SMBCLK High250ns (min)
tHD:DATData Out Hold Time after SMBCLK Low300
930		ns (min)
ns (max)
tHD:STAHold Time after (Repeated) Start Condition. After this period the first clock is generated.4.0µs (min)
tSU:STOStop Condition SMBCLK High to SMBDAT Low (Stop Condition Setup)100ns (min)
tSU:STASMBus Repeated Start-Condition Setup Time, SMBCLK High to SMBDAT Low4.7µs (min)
tBUFSMBus Free Time between Stop and Start Conditions4.7µs (min)
(1) Limits are guaranteed to TI's AOQL (Average Outgoing Quality Level).
(2) The output rise time is measured from (VIL max - 0.15 V) to (VIH min + 0.15 V).
(3) The output fall time is measured from (VIH min + 0.15 V) to (VIL min - 0.15 V).
(4) Holding the SMBData and/or SMBCLK lines Low for a time interval greater than tTIMEOUT will reset the LM64’s SMBus state machine, therefore setting SMBDAT and SMBCLK pins to a high impedance state.
GUID-4AF63E26-47B6-481D-928C-57DF40B190AC-low.gifFigure 5-1 SMBus Timing Diagram for SMBCLK and SMBDAT Signals
Table 5-1
Pin NamePin #D1D2D3D4D5D6R1SNPESD CLAMP
GPIO11XXX
GPIO22XXX
GPIO33XXX
PWM4XXX
VDD5X
D+6XXXXXX
D−7XXXXXX
T_Crit8XXXX
A012X
ALERT14XXXX
TACH15XXX
SMBDAT16XXX
SMBCLK17X
GPIO518XXX
GPIO419XXX
GPD120X
GPD221X
GPD322X
GPD423X
GPD524X
GUID-E542AB1B-0BA1-46DC-BB57-2D65C546A7FF-low.gifFigure 5-2 ESD Protection Input Structure