SNVSBW0B October 2022 – August 2024 LM64440-Q1 , LM64460-Q1
PRODUCTION DATA
Parameter | Test Condition | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
SWITCH NODE | ||||||
tON(min) | Minimum HS switch on time | VIN = 20V, IOUT = 2A | 55 | 70 | ns | |
tON(max) | Maximum HS switch on time | 9 | μs | |||
tOFF(min) | Minimum LS switch on time | VIN = 4V, IOUT = 1A | 65 | 85 | ns | |
tSS | Time from first SW pulse to Vref at 90% | VIN ≥ 4.2V | 2 | 3 | 4 | ms |
tSS2 | Time from first SW pulse to release of FPWM lockout if output not in regulation | VIN ≥ 4.2V | 4.5 | 6.5 | 8.5 | ms |
tW | Short circuit wait time ("hiccup" time) | 40 | ms | |||
ENABLE | ||||||
tEN | Turn-on delay(1) | CVCC = 1µF, time from EN high to first SW pulse if output starts at 0V | 0.7 | ms | ||
tB | Blanking of EN after rising or falling edges | Low level is 0.6V | 4 | 8 | µs | |
SYNC | ||||||
tPULSE_H | High duration needed to be recognized as a pulse | 100 | ns | |||
tPULSE_L | Low duration needed to be recognized as a pulse | 100 | ns | |||
tMODE | Time at one level needed to indicate FPWM or AUTO mode | 16.5 | µs | |||
tSYNC | High or low signal duration in a valid synchronization signal | 8 | µs | |||
tMEAS | MODE/SYNC pin duration of resistance test upon entering AUTO mode | Level-dependent MODE/SYNC pin operation | 25 | µs | ||
POWER GOOD | ||||||
tPGDFLT(rise) | Delay time to PGOOD high signal | 1.5 | 2 | 2.5 | ms | |
tPGDFLT(fall) | Glitch filter time constant for PGOOD function | 24 | µs |