SNVSBW0A October   2022  – October 2023 LM64460-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
    1. 6.1 Wettable Flanks
    2. 6.2 Pinout Design for Clearance and FMEA
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Characteristics
    7. 7.7 Systems Characteristics
    8. 7.8 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Input Voltage Range (VIN1, VIN2)
      2. 8.3.2  Output Voltage Setpoint (FB)
      3. 8.3.3  Precision Enable and Input Voltage UVLO (EN)
      4. 8.3.4  MODE/SYNC Operation
        1. 8.3.4.1 Level-Dependent MODE/SYNC Control
        2. 8.3.4.2 Pulse-Dependent MODE/SYNC Control
      5. 8.3.5  Clock Locking
      6. 8.3.6  Power-Good Monitor (PGOOD)
      7. 8.3.7  Bias Supply Regulator (VCC, BIAS)
      8. 8.3.8  Bootstrap Voltage and UVLO (CBOOT)
      9. 8.3.9  Spread Spectrum
      10. 8.3.10 Soft Start and Recovery From Dropout
      11. 8.3.11 Overcurrent and Short-Circuit Protection
      12. 8.3.12 Thermal Shutdown
      13. 8.3.13 Input Supply Current
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Active Mode
        1. 8.4.3.1 CCM Mode
        2. 8.4.3.2 AUTO Mode – Light-Load Operation
          1. 8.4.3.2.1 Diode Emulation
          2. 8.4.3.2.2 Frequency Foldback
        3. 8.4.3.3 FPWM Mode – Light-Load Operation
        4. 8.4.3.4 Minimum On-Time (High Input Voltage) Operation
        5. 8.4.3.5 Dropout
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design 1 – Automotive Synchronous Buck Regulator at 2.1 MHz
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1  Custom Design With WEBENCH® Tools
          2. 9.2.1.2.2  Setting the Output Voltage
          3. 9.2.1.2.3  Choosing the Switching Frequency
          4. 9.2.1.2.4  Inductor Selection
          5. 9.2.1.2.5  Output Capacitor Selection
          6. 9.2.1.2.6  Input Capacitor Selection
          7. 9.2.1.2.7  Bootstrap Capacitor
          8. 9.2.1.2.8  VCC Capacitor
          9. 9.2.1.2.9  BIAS Power Connection
          10. 9.2.1.2.10 Feedforward Network
          11. 9.2.1.2.11 Input Voltage UVLO
        3. 9.2.1.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Thermal Design and Layout
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Development Support
        1. 10.1.2.1 Custom Design With WEBENCH® Tools
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.4.3.3 FPWM Mode – Light-Load Operation

Like AUTO mode operation, select FPWM operation using the MODE/SYNC pin. FPWM applies by default during synchronization. In FPWM mode, the switching frequency is maintained constant while lightly loaded by allowing negative current to flow in the inductor. Negative current is limited to –3 A by a reverse current limit circuit.

GUID-20210607-CA0I-TF50-VRNP-99RKB7QCZVST-low.svg
In FPWM mode, continuous conduction (CCM) is possible even if IOUT is less than half of Iripple.
Figure 8-23 FPWM Mode Operation

Transitions between AUTO mode and FPWM mode can be commanded during operation. Such transitions are gradual, taking tens of clock cycles, allowing minimal disruption of the output voltage during transitions. If the load is heavy enough to operate in CCM, because operation is identical in FPWM and AUTO modes, no change in behavior is visible until the next time the circuit is lightly loaded.

Frequency reduction is still available in FPWM mode if the output voltage is high enough to command minimum on time even while lightly loaded, allowing good behavior during faults that involve the output being pulled up.