SNVSBW0B October   2022  – August 2024 LM64440-Q1 , LM64460-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
    1. 5.1 Wettable Flanks
    2. 5.2 Pinout Design for Clearance and FMEA
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Characteristics
    7. 6.7 Systems Characteristics
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Voltage Range (VIN1, VIN2)
      2. 7.3.2  Output Voltage Setpoint (FB)
      3. 7.3.3  Precision Enable and Input Voltage UVLO (EN)
      4. 7.3.4  MODE/SYNC Operation
        1. 7.3.4.1 Level-Dependent MODE/SYNC Control
        2. 7.3.4.2 Pulse-Dependent MODE/SYNC Control
      5. 7.3.5  Clock Locking
      6. 7.3.6  Power-Good Monitor (PGOOD)
      7. 7.3.7  Bias Supply Regulator (VCC, BIAS)
      8. 7.3.8  Bootstrap Voltage and UVLO (CBOOT)
      9. 7.3.9  Spread Spectrum
      10. 7.3.10 Soft Start and Recovery From Dropout
      11. 7.3.11 Overcurrent and Short-Circuit Protection
      12. 7.3.12 Thermal Shutdown
      13. 7.3.13 Input Supply Current
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Active Mode
        1. 7.4.3.1 CCM Mode
        2. 7.4.3.2 AUTO Mode – Light-Load Operation
          1. 7.4.3.2.1 Diode Emulation
          2. 7.4.3.2.2 Frequency Foldback
        3. 7.4.3.3 FPWM Mode – Light-Load Operation
        4. 7.4.3.4 Minimum On-Time (High Input Voltage) Operation
        5. 7.4.3.5 Dropout
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design 1 – Automotive Synchronous 6A Buck Regulator at 2.1MHz
        1. 8.2.1.1 Design Requirements
      2. 8.2.2 Design 2 – Automotive Synchronous 4A Buck Regulator at 2.1MHz
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1  Custom Design With WEBENCH® Tools
          2. 8.2.2.2.2  Setting the Output Voltage
          3. 8.2.2.2.3  Choosing the Switching Frequency
          4. 8.2.2.2.4  Inductor Selection
          5. 8.2.2.2.5  Output Capacitor Selection
          6. 8.2.2.2.6  Input Capacitor Selection
          7. 8.2.2.2.7  Bootstrap Capacitor
          8. 8.2.2.2.8  VCC Capacitor
          9. 8.2.2.2.9  BIAS Power Connection
          10. 8.2.2.2.10 Feedforward Network
          11. 8.2.2.2.11 Input Voltage UVLO
        3. 8.2.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Thermal Design and Layout
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
      2. 9.1.2 Development Support
        1. 9.1.2.1 Custom Design With WEBENCH® Tools
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.6 Power-Good Monitor (PGOOD)

The PGOOD function is implemented to replace a discrete reset device, reducing BOM count and cost. The PGOOD voltage goes low when the feedback (FB) voltage is outside of the specified PGOOD thresholds (see Figure 6-8). This can occur during current limit and thermal shutdown, as well as when disabled and during normal start-up. A glitch filter prevents false flag operation for short excursions of the output voltage, such as during line and load transients. Output voltage excursions that are shorter than tPGDFLT(fall) do not trip the PGOOD flag. Refer to Figure 7-13 to best understand PGOOD operation.

The PGOOD output consists of an open-drain N-channel transistor, requiring an external pullup resistor to a suitable logic supply or VOUT. When EN is pulled low, the flag output is also forced low. With EN low, PGOOD remains valid as long as the input voltage is above 1V (typical).

LM64440-Q1 LM64460-Q1 PGOOD Timing Diagram (Excludes OV Events)Figure 7-13 PGOOD Timing Diagram (Excludes OV Events)
Table 7-3 Conditions That Cause PGOOD to Signal a Fault (Pull Low)
FAULT CONDITION INITIATEDFAULT CONDITION ENDS (AFTER WHICH tPGDFLT(rise) MUST PASS BEFORE PGOOD OUTPUT IS RELEASED)(1)
VOUT < VOUT-target × PGDUV AND t > tPGDFLT(fall)Output voltage in regulation:
VOUT-target × (PGDUV + PGDHYST) < VOUT < VOUT-target × (PGDOV – PGDHYST) (see Figure 6-8)
VOUT > VOUT-target × PGDOV AND t > tPGDFLT(fall)Output voltage in regulation
TJ > TSHDTJ < TSHD-F AND output voltage in regulation
VEN < VEN-TH fallingVEN > VEN-TH rising AND output voltage in regulation
VCC < VCC-UVLO - VCC-UVLO-HYSTVCC > VCC-UVLO AND output voltage in regulation
(1) As an additional operational check, PGOOD remains low during the soft-start time, which is defined as the time for the output voltage to reach the setpoint or tSS2 has passed since initiation (whichever is lower).